Distributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

A striped inductor and its utilization of a voltage-controlled oscillator (VCO) are studied with the aim of suppressing phase noise degradation in K- and Ka-bands. The proposed striped inductor exhibits reduced series resistance in the high frequency region by increasing the cross-sectional peripheral length, as with the Litz wire, and the VCO of the striped inductor simultaneously exhibits a lower phase noise than that of the conventional inductor. Striped and conventional inductors and VCOs are designed and fabricated, and their use of K- and Ka-bands is measured. Results show that the Q factor and corner frequency of the striped inductor are approximately 1.3 and 1.6 times higher, respectively, than that of the conventional inductor. Moreover, the 1-MHz-offset phase noise of the striped inductor's VCO in the K- and Ka-bands was approximately 3.5 dB lower than that of the conventional inductor. In this study, a 65-nm standard CMOS process was used.

This paper analyzes three passive noise shaping techniques in a SAR ADC. These passive noise shaping techniques can realize 1^st and 2^nd order noise shaping. These proposed opamp-less noise shaping techniques are realized by charge-redistribution. This means that the proposals maintain the basic architecture and operation principle of a charge-redistribution SAR ADC. Since the proposed techniques work in a passive mode, the proposals have high power efficiency. Meanwhile, the proposed noise shaping SAR ADCs are robust to feature size scaling and power supply reduction. Flicker noise is not introduced into the ADC by passive noise shaping techniques. Therefore, no additional calibration techniques for flicker noise are required. The noise shaping effects of the 1^st and 2^nd order noise shaping are verified by behavioral simulation results. The relationship between resolution improvement and oversampling rate is also explored in this paper.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm² chip area only.

This paper proposes two linearity enhancement techniques for open-loop amplifiers. One technique is nonlinearity cancellation. An amplifier with reversed nonlinearity is proposed to cascade with a conventional common source amplifier. The product of these two nonlinear gains demonstrates much higher linearity. It achieves a SFDR of 71 dB when differential output range is 600 mV. Compared with the conventional common source amplifier, about 24 dB improvement is achieved. Another proposed technique is gain adapting. An input amplitude detector utilizing second order nonlinearity is combined with a source-degenerated amplifier. It can adjust the gain automatically according to the input amplitude, and compensate the gain compression when the input amplitude becomes larger. A SFDR of 69 dB is realized when the differential output range is 600 mV. An improvement of 23 dB is achieved after gain is adapted. Furthermore, mismatch calibration for the two proposed linearity enhancement techniques is investigated. Finally, comparison between two proposed amplifiers is introduced. The amplifier with nonlinearity cancellation has advantage in large signal range while the amplifier utilizing gain adapting is more competitive on accurate calibration, fast response and low noise.

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm² is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.

This paper presents analysis and simple design guideline for ThruChip Interface (TCI) as located by LC-VCO which is used in high-speed SoC. The electromagnetic interference (EMI) from TCI channels to LC-VCO is analyzed and evaluated. The accuracy of the analysis and design guidelines is verified through the test-chip verification.

In this study, a well-shaped microelectrode array (MEA) for fabricating a high-density complementary metal-oxide semiconductor amperometric electrochemical sensor array was designed and verified. By integrating an auxiliary electrode with the well-shaped structure of the MEA, the footprint was reduced and high density and high resolution were also achieved. The results of three-dimensional electrochemical simulations confirmed the effectiveness of the proposed MEA structure and possibility of increasing the density to four times than that achieved by the conventional two-dimensional structure.

In this paper, we propose improved methods of liquid-phase detection of biological targets utilizing magnetic markers and a high-critical-temperature superconducting quantum interference device (SQUID). For liquid-phase detection, the bound and unbound (free) markers are magnetically distinguished by using Brownian relaxation of free markers. Although a signal from the free markers is zero in an ideal case, it exists in a real sample on account of the aggregation and precipitation of free markers. This signal is called a blank signal, and it degrades the sensitivity of target detection. To solve this problem, we propose improved detection methods. First, we introduce a reaction field, B_re, during the binding reaction between the markers and targets. We additionally introduce a dispersion process after magnetization of the bound markers. Using these methods, we can obtain a strong signal from the bound markers without increasing the aggregation of the free markers. Next, we introduce a field-reversal method in the measurement procedure to differentiate the signal from the markers in suspension from that of the precipitated markers. Using this procedure, we can eliminate the signal from the precipitated markers. Then, we detect biotin molecules by using these methods. In an experiment, the biotins were immobilized on the surfaces of large polymer beads with diameters of 3.3 µm. They were detected with streptavidin-conjugated magnetic markers. The minimum detectable molecular number concentration was 1.8×10^-19 mol/ml, which indicates the high sensitivity of the proposed method.

One of the fundamental problems in many-pixel detectors implemented in cryogenics environments is the number of bias and read-out wires. If one targets a megapixel range detector, number of wires should be significantly reduced. One possibility is that the detectors are serially connected and biased by using only one line and read-out is accomplished by on-chip circuitry. In addition to the number of pixels, the detectors should have fast response times, low dead times, high sensitivities, low inter-pixel crosstalk and ability to respond to simultaneous irradiations to individual pixels for practical purposes. We have developed an equivalent circuit model for a serially connected superconducting strip line detector (SSLD) array together with the read-out electronics. In the model we take into account the capacitive effects due to the ground plane under the detector, effects of the shunt resistors fabricated under the SSLD layer, low pass filters placed between the individual pixels that enable individual operation of each pixel and series resistors that prevents the DC bias current flowing to the read-out electronics as well as adjust the time constants of the inductive SSLD loop. We explain the results of investigation of the following parameters: Crosstalk between the neighbor pixels, response to simultaneous irradiation, dead times, L/R time constants, low pass filters, and integration with the SFQ front-end circuit. Based on the simulation results, we show that SSLDs are promising devices for detecting a wide range of incident radiation such as neurons, X-rays and THz waves in many-pixel configurations.

We describe a calculation tool and modeling methods to find self and mutual inductance and current distribution in superconductive multilayer circuit layouts. Accuracy of the numerical solver is discussed and compared with experimental measurements. Effects of modeling parameter selection on calculation results are shown, and we make conclusions on the selection of modeling parameters for fast but sufficiently accurate calculations when calibration methods are used. Circuit theory for the calculation of branch impedances from the output of the numerical solver is discussed, and compensation for solution difficulties is shown through example. We elaborate on the construction of extraction models for superconductive integrated circuits, with and without resistive branches. We also propose a method to calculate current distribution in a multilayer circuit with multiple bias current feed points. Finally, detailed examples are shown where the effects of stacked vias, bias pillars, coupling, ground connection stacks and ground return currents in circuit layouts for the AIST advanced process (ADP2) and standard process (STP2) are analyzed. We show that multilayer inductance and current distribution extraction in such circuits provides much more information than merely branch inductance, and can be used to improve layouts; for example through reduced coupling between conductors.

A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm² Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm² 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.

We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.

We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mV_pp, and so we successfully reduced the required read bitline signal from 250 to 70 mV_pp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.

This paper presents a novel data compression method for testing integrated circuits within the selective dictionary coding framework. Due to the inverse value of dictionary indices made use of for the compatibility analysis with the heuristic algorithm utilized to solve the maximum clique problem, the method can obtain a higher compression ratio than existing ones.