A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills

Atsushi KUROKAWA; Toshiki KANAMOTO; Akira KASEBE; Yasuaki INOUE; Hiroo MASUDA

doi:10.1093/ietfec/e88-a.11.3180

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills

Atsushi KUROKAWA, Toshiki KANAMOTO, Akira KASEBE, Yasuaki INOUE, Hiroo MASUDA

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We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.11 pp.3180-3187

Publication Date: 2005/11/01

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DOI: 10.1093/ietfec/e88-a.11.3180

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Atsushi KUROKAWA, Toshiki KANAMOTO, Akira KASEBE, Yasuaki INOUE, Hiroo MASUDA, "A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 11, pp. 3180-3187, November 2005, doi: 10.1093/ietfec/e88-a.11.3180.
Abstract: We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.11.3180/_p

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@ARTICLE{e88-a_11_3180,
author={Atsushi KUROKAWA, Toshiki KANAMOTO, Akira KASEBE, Yasuaki INOUE, Hiroo MASUDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills},
year={2005},
volume={E88-A},
number={11},
pages={3180-3187},
abstract={We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.},
keywords={},
doi={10.1093/ietfec/e88-a.11.3180},
ISSN={},
month={November},}

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TY - JOUR
TI - A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3180
EP - 3187
AU - Atsushi KUROKAWA
AU - Toshiki KANAMOTO
AU - Akira KASEBE
AU - Yasuaki INOUE
AU - Hiroo MASUDA
PY - 2005
DO - 10.1093/ietfec/e88-a.11.3180
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2005
AB - We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.
ER -