A Fast Delay Computation for the Hybrid Structured Clock Network

Yi ZOU; Yici CAI; Qiang ZHOU; Xianlong HONG; Sheldon X.-D. TAN

doi:10.1093/ietfec/e88-a.7.1964

A Fast Delay Computation for the Hybrid Structured Clock Network

Yi ZOU, Yici CAI, Qiang ZHOU, Xianlong HONG, Sheldon X.-D. TAN

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This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.7 pp.1964-1970

Publication Date: 2005/07/01

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DOI: 10.1093/ietfec/e88-a.7.1964

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Yi ZOU, Yici CAI, Qiang ZHOU, Xianlong HONG, Sheldon X.-D. TAN, "A Fast Delay Computation for the Hybrid Structured Clock Network" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 7, pp. 1964-1970, July 2005, doi: 10.1093/ietfec/e88-a.7.1964.
Abstract: This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.7.1964/_p

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@ARTICLE{e88-a_7_1964,
author={Yi ZOU, Yici CAI, Qiang ZHOU, Xianlong HONG, Sheldon X.-D. TAN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Delay Computation for the Hybrid Structured Clock Network},
year={2005},
volume={E88-A},
number={7},
pages={1964-1970},
abstract={This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.},
keywords={},
doi={10.1093/ietfec/e88-a.7.1964},
ISSN={},
month={July},}

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TY - JOUR
TI - A Fast Delay Computation for the Hybrid Structured Clock Network
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1964
EP - 1970
AU - Yi ZOU
AU - Yici CAI
AU - Qiang ZHOU
AU - Xianlong HONG
AU - Sheldon X.-D. TAN
PY - 2005
DO - 10.1093/ietfec/e88-a.7.1964
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2005
AB - This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.
ER -