An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

Yu HOU; Takamoto WATANABE; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transfun.E98.A.466

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

Yu HOU, Takamoto WATANABE, Masaya MIYAHARA, Akira MATSUZAWA

Full Text Views

0

Share
Cite this

Summary :

An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm². It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.2 pp.466-475

Publication Date: 2015/02/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.466

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

Category

Authors

Yu HOU
  TokyoInstitute of Technology
Takamoto WATANABE
  DENSO CORPORATION
Masaya MIYAHARA
  TokyoInstitute of Technology
Akira MATSUZAWA
  TokyoInstitute of Technology

Keyword

all-digital, reconfigurable resolution, TAD, low-voltage, sensor interface

Cite this

Copy

Yu HOU, Takamoto WATANABE, Masaya MIYAHARA, Akira MATSUZAWA, "An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 2, pp. 466-475, February 2015, doi: 10.1587/transfun.E98.A.466.
Abstract: An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm². It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.466/_p

Copy

@ARTICLE{e98-a_2_466,
author={Yu HOU, Takamoto WATANABE, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology},
year={2015},
volume={E98-A},
number={2},
pages={466-475},
abstract={An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm². It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.},
keywords={},
doi={10.1587/transfun.E98.A.466},
ISSN={1745-1337},
month={February},}

Copy

TY - JOUR
TI - An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 466
EP - 475
AU - Yu HOU
AU - Takamoto WATANABE
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2015
DO - 10.1587/transfun.E98.A.466
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2015
AB - An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm². It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.
ER -