This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz), 48.5% power consumption reduction (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4 mW and the max-performance is decreased to 2.08because of the increased computation workload.

In this paper, we use frequency-domain equalization (FDE) to create coherent optical single-carrier (CO-SC) transmission systems that are very tolerant of chromatic dispersion (CD) and polarization mode dispersion (PMD). The efficient transmission of a 25-Gb/s NRZ-QPSK signal by using the proposed FDE is demonstrated under severe CD and PMD conditions. We also discuss the principle of FDE and some techniques suitable for implementing CO-SC-FDE. The results show that a CO-SC-FDE system is very tolerant of CD and PMD and can achieve high transmission rates over single mode fiber without optical dispersion compensation.

An efficient back-bias (Vbb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a Vbb level of 1.44 V at Vcc1.5 V, compared to a conventional system in which Vbb only reaches 0.6 V. HPC can pump without the threshold voltage (Vth) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAM's, because a Vbb level lower than 1.0 V is necessary to meet the limitations of the Vth of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.

Music is often used for emotion induction because it can change the emotions of people. However, since we subjectively feel different emotions when listening to music, we propose an emotion induction system that generates music that is adapted to each individual. Our system automatically generates suitable music for emotion induction based on the emotions predicted from an electroencephalogram (EEG). We examined three elements for constructing our system: 1) a music generator that creates music that induces emotions that resemble the inputs, 2) emotion prediction using EEG in real-time, and 3) the control of a music generator using the predicted emotions for making music that is suitable for inducing emotions. We constructed our proposed system using these elements and evaluated it. The results showed its effectiveness for inducing emotions and suggest that feedback loops that tailor stimuli to individuals can successfully induce emotions.

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (Dll) for deskew, and a frequency-locked loop(FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector newly developed which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4µm CMOS technology is used to fabricate the chip.

Homotopy methods are known to be effective methods for finding DC operating points of nonlinear circuits with the theoretical guarantee of global convergence. There are several types of homotopy methods; as one of the most efficient methods for solving bipolar transistor circuits, the variable-gain homotopy (VGH) method is well-known. In this paper, we propose an efficient VGH method for solving bipolar and MOS transistor circuits. We also show that the proposed method converges to a stable operating point with high possibility from any initial point. The proposed method is not only globally convergent but also more efficient than the conventional VGH methods. Moreover, it can easily be implemented in SPICE.

To enhance the throughput of wireless local area networks (WLANs) by efficiently utilizing the radio resource, a distributed coordination function-based (DCF-based) orthogonal frequency division multiple access (OFDMA) WLAN system has been proposed. In the system, since each OFDMA sub-channel is assigned to the associated station with the highest channel gain, the transmission rate of DATA frames can be enhanced thanks to multi-user diversity. However, the optimum allocation of OFDMA sub-channels requires the estimation of channel state information (CSI) of all associated stations, and this incurs excessive signaling overhead. As the number of associated stations increases, the signaling overhead severely degrades the throughput of DCF-based OFDMA WLAN. To reduce the signaling overhead while obtaining a sufficient diversity gain, this paper proposes a channel access scheme that performs multiple DCF-based channel access. The key idea of the proposed scheme is to introduce additional DCF-based prioritized access along with the traditional DCF-based random access. In the additional DCF-based prioritized access, by dynamically adjusting contention window size according to the CSI of each station, only the stations with better channel state inform their CSI to the access point (AP), and the signaling overhead can be reduced while maintaining high multi-user diversity gain. Numerical results confirm that the proposed channel access scheme enhances the throughput of OFDMA WLAN.

The performance of devices based on two dimensional (2D) materials is significantly affected upon prolonged exposure to atmosphere. We analyzed time based environmental degradation of electrical properties of HfS2 field effect transistors. Atmospheric entities like oxygen and moisture adversely affect the device surface and reduction in drain current is observed over period of 48 hours. Two corrective measures, namely, PMMA passivation and vacuum annealing, have been studied to address the diminution of current by contaminants. PMMA passivation prevents the device from environment and reduces the effect of Coulomb scattering. Improvement in current characteristics signifies the importance of dielectric passivation for 2D materials. On the other hand, vacuum annealing is useful in removing contaminants from the affected surface. In order to figure out optimum process conditions, properties have been studied at various annealing temperatures. The improvement in drain current level was observed upon vacuum annealing within optimum range of annealing temperature.

Recently, there are so many researches on Autonomous Distributed Manufacturing Systems (ADMSs), where cooperation among agents is used to solve problems, such as the scheduling problem and the vehicle routing problem. We target ADMSs where an ADMS consists of two sub-systems: a Production System (PS) and an Autonomous Transportation System (ATS). This paper discusses an on-line Tasks Assignment and Routing Problem (TARP) for ATSs under conditions of given production schedule and finite buffer capacity. The TARP results in a constrained version of the Pickup and Delivery Problem with Time Windows (PDPTW), and this paper gives a mathematical formulation of the problem. This paper, also, proposes a cooperative algorithm to obtain suboptimal solutions in which no deadlocks and buffer overflows occur. By computational experiments, we will examine the effectiveness of the proposed algorithm. Computational experiments show that the proposed algorithm is able to obtain efficient and deadlock-free routes even though the buffer capacity is less.

Novel gain monitoring scheme in Remotely-Pumped EDF/DRA hybrid inline amplifier is proposed using Optical Time Domain Reflectometer (OTDR). Signal degradation due to cross gain modulation (XGM) caused by an OTDR pulse in the distributed Raman amplifier (DRA) section and remotely-pumped EDF (RP-EDF) unit is analyzed theoretically. The required conditions for suppressing of XGM in the DRA section are derived. We propose the directional bypass configuration to realize OTDR measurement without XGM in the EDF unit. Transmission experiments using the RP-EDF/DRA hybrid inline amplifier demonstrate the absence of transmission impairement induced by OTDR. An analysis of the OTDR trace for each gain medium is also discussed. The theoretical analysis agrees well with the experimental result.

Mass transport was first employed in an OMVPE system for 1.55 µm GaInAsP/InP laser. The wafers grown by OMVPE were treated at 700 under cracked PH3 and H2+N2 atmosphere for 1 hr, resulting in buried structure and the BH laser showed low threshold current of 50 mA (pulsed) without optimization.

The delay time component (τs) of an InGaAs MOSFET caused by dynamic source resistance is discussed. On the basis of the relationship between the current density (J) and the dynamic source resistance (rs), the value of rs is proportional to 1/J with some offset at low current densities, whereas the offset becomes smaller in a region of high current density. The value of τs depends on the current in a way similar to rs. Because the offset in the high-current-density region is proportional to the square root of the effective mass, an InGaAs MOSFET with a small mass has a shorter rs than a Si MOSFET.

Recently, many researchers tackle accurate object recognition algorithms and many algorithms are proposed. However, these algorithms have some problems caused by variety of real environments such as a direction change of the object or its shading change. The new tracking algorithm, Cascade Particle Filter, is proposed to fill such demands in real environments by constructing the object model while tracking the objects. We have been investigating to implement accurate object recognition on embedded systems in real-time. In order to apply the Cascade Particle Filter to embedded applications such as surveillance, automotives, and robotics, a hardware accelerator is indispensable because of limitations in power consumption. In this paper we propose a hardware implementation of the Discrete AdaBoost algorithm that is the most computationally intensive part of the Cascade Particle Filter. To implement the proposed hardware, we use PICO Express, a high level synthesis tool provided by Synfora, for rapid prototyping. Implementation result shows that the synthesized hardware has 1,132,038 transistors and the die area is 2,195 µm 1,985 µm under a 0.180 µm library. The simulation result shows that total processing time is about 8.2 milliseconds at 65 MHz operation frequency.

This paper discusses a computer-aided network planning support system called PIGEON that has been developed primarily for advancing countries implementing the applicability to various types of networks and the supportability to the sensitivity analysis. For the implementation of the applicability, the customization by reflecting existing network facilities and their accompanying restrictive conditions into a design result is focused. A case study on the customization shows the effectiveness of the reflection. The procedures are given of the sensitivity analysis in order to examine and to evaluate the effect of the uncertain factors in network planning. In particular, a method called "network modification" is proposed for the sensitivity analysis for uncertain factors associated with a partial network. The network modification efficiently integrates network planner's judgments into a design result by the interactive method. In addition, this paper describes the importance of streamlining the data input and the evaluation of design results, showing the operating time required for each work phase in network planning.

This paper proposes an algorithm for analyzing the reachability property of Petri nets by the use of unfoldings. It is known that analyzing the reachability by using unfoldings requires exponential time and space to the size of unfolding. The algorithm is based on the branch and bound technique, and experimental results show efficiency of the algorithm.

The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.

This paper discusses an on-line Tasks Assignment and Routing Problem (TARP) for Autonomous Transportation Systems (ATSs) in manufacturing systems. The TARP is a constrained version of the Pickup and Delivery Problem with Time Windows (PDPTW). In our former study, a cooperative algorithm, called the triple loop method, with autonomous distributed agents has been proposed. The Improving initial Task Assignment and Avoiding Deadlock method (ITAAD) is a faster algorithm than the triple loop method. In this paper, we propose a new vehicle routing method for the ITAAD. Results of computational experiments show effectiveness of the proposed routing method.

In this paper, we represent a class structure using directed graph in which each node corresponds to each member of the class. To quantify the dependence relationship among members, we define weighted closure. Using this quantified relationship and effort equation proposed by M. H. Halstead, we propose a metric for class structural complexity.

Micro-tribology is a key technology in micro-machine. Atomic-scale wear and friction fluctuations degrade the performance of micro-machines. New wear-resistant, low friction materials should be useful in reducing micro- and macro-tribological wear and friction fluctuations. Our investigation of the frictional characteristics of polished CVD diamond films by FFM (friction force microscope), AFM (atomic force microscope) and conventional reciprocating tribometer and trial micro processing of diamond produced three main results. First, the friction coefficient of diamond film increases rapidly with decreasing load in the micro-load region. This is partially due to the surface tension of adsorbed water on the surface under high humidity. In the macro-load region also, the friction coefficient increases with decreasing load, but, in this case it is due to elastic deformation. The second result is that diamond film has excellent wear resistance in the micro-load region compared with silicon and diamond-like carbon (DLC) film. Finally, a micro-diamond gear and diamond shaft were fabricated by laser machining and thermo-chemical etching, and then assembled.