Hot carrier effects in narrow-channel MOSETs are investigated. With decreasing channel width below 1µm, the ratio of substrate to channel currents show marked increase. By using the newly developed full three-dimensional process/device simulation system, two significant causes of the hot carrier effects are clarified.

The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

Anomalous leakage current which flows between source and drain in thin film SOI MOSFET's is investigated. It is confirmed that the leakage current is caused by enhanced diffusion of the source/drain dopants along the LOCOS-induced crystal defects. Stress analysis by 2D simulation reveals that thinning a buried-oxide effectively suppresses deformation of an SOI film associated with over-oxidation during LOCOS. It is experimentally confirmed that using a SIMOX substrate which has a thinner buried-oxide causes no noticeable deformation of the SOI film nor anomalous leakage current.

The velocity overshoot and hot carrier effects in thin-film SOI-nMOSFETs have been studied using a two-dimensional device simulator based on the energy transport model. It has been found that the velocity overshoot effect in a nearly-intrinsic device becomes pronounced in the short channel region because of their high carrier mobility. The distribution of the electron velocity in a 0.2 µm channel length SOI device shows that the velocity overshoot takes place over the whole channel region, which enhances the drive capability significantly. The behaviors of hot carriers injected into the gate oxide and the back oxide have been simulated for the first time by using the energy distribution functions of electrons and holes at the SOI-SiO2 interface and solving the current continuity equation in the oxide layer. It has been found that hot carriers are injected not only into the gate oxide but also into the back oxide, which can degrade hot-carrier reliability in small-featured thin-film SOI-MOSFETs.