An Ultra Low Voltage SOI CMOS Pass-Gate Logic

Tsuneaki FUSE; Yukihito OOWAKI; Mamoru TERAUCHI; Shigeyoshi WATANABE; Makoto YOSHIMI; Kazunori OHUCHI; Jun'ichi MATSUNAGA

An Ultra Low Voltage SOI CMOS Pass-Gate Logic

Tsuneaki FUSE, Yukihito OOWAKI, Mamoru TERAUCHI, Shigeyoshi WATANABE, Makoto YOSHIMI, Kazunori OHUCHI, Jun'ichi MATSUNAGA

Full Text Views

0

Share
Cite this

Summary :

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.3 pp.472-477

Publication Date: 1997/03/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)

Category

Cite this

Copy

Tsuneaki FUSE, Yukihito OOWAKI, Mamoru TERAUCHI, Shigeyoshi WATANABE, Makoto YOSHIMI, Kazunori OHUCHI, Jun'ichi MATSUNAGA, "An Ultra Low Voltage SOI CMOS Pass-Gate Logic" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 3, pp. 472-477, March 1997, doi: .
Abstract: An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e80-c_3_472/_p

Copy

@ARTICLE{e80-c_3_472,
author={Tsuneaki FUSE, Yukihito OOWAKI, Mamoru TERAUCHI, Shigeyoshi WATANABE, Makoto YOSHIMI, Kazunori OHUCHI, Jun'ichi MATSUNAGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Ultra Low Voltage SOI CMOS Pass-Gate Logic},
year={1997},
volume={E80-C},
number={3},
pages={472-477},
abstract={An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.},
keywords={},
doi={},
ISSN={},
month={March},}

Copy

TY - JOUR
TI - An Ultra Low Voltage SOI CMOS Pass-Gate Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 472
EP - 477
AU - Tsuneaki FUSE
AU - Yukihito OOWAKI
AU - Mamoru TERAUCHI
AU - Shigeyoshi WATANABE
AU - Makoto YOSHIMI
AU - Kazunori OHUCHI
AU - Jun'ichi MATSUNAGA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1997
AB - An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.
ER -