In the case of rigid disk files, improvements in the recording medium and the head are required to increase bit density. This letter reports a high recording density of 2600 bit/mm (65000 bit/i), achieved by using high coercive force (100 Oe) sputtered γ-Fe2O3 thin film media and a narrow gap (2g0.15µm)head.

Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.

Gamma ferric oxide thin film media with a thickness of 0.190.27 µm were prepared by a reactive RF sputtering. Signal output loss with increasing temperature at high recording density was studies. Heating a medium-head system to 55 results in a 16% loss of signal output at 790 bpm (D-6 dB) of recording density for a medium having a 0.19 µm thickness; a 40% loss of signal output for a conventional-coated medium having a 0.7 µm thickness at 400 bpm (D-6dB), accompanying a decrease of a saturation write current value, IW(k-1) (an optimum write current). Increments of medium thickness and write current enhanced the thermal signal output loss. An over-saturated recording in the write process was suggested to cause the thermal signal output loss, especially for the thicker media. From the perspective of thermal stability of signal output at high recording density, sputtered γ-Fe2O3 thin film media are advantageous because of their thinness and small write current dependence of signal output.

Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.

In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

In the acoustic echo canceller (AEC), the step-size parameter of the adaptive filter must be varied according to the situation if double talk occurs and/or the echo path changes. We propose an AEC that uses a sub-adaptive filter. The proposed AEC can control the step-size parameter according to the situation. Moreover, it offers superior convergence compared to the conventional AEC even when the double talk and the echo path change occur simultaneously. Simulations demonstrate that the proposed AEC can achieve higher ERLE and faster convergence than the conventional AEC. The computational complexity of the proposed AEC can be reduced by reducing the number of taps of the sub-adaptive filter.

In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

This paper introduces the concept of hierarchical testability of data paths for delay faults. A definition of hierarchically two-pattern testable (HTPT) data path is developed. Also, a design for testability (DFT) method is presented to augment a data path to become an HTPT one. The DFT method incorporates a graph-based analysis of an HTPT data path and makes use of some graph algorithms. The proposed method can provide similar advantages to the enhanced scan approach at a much lower hardware overhead cost.

This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.

The thickness dependence of structure, magnetic properties and read-write characteristics has been studied for sputtered iron oxide thin films prepared by RF reactive sputtering. For sputter-deposited Fe3O4 films, [111] preferential orientation perpendicular to film surface is improved and crystal size increases with an increase in thickness (δ). Magnetic properties for Fe3O4 films are affected by thickness. In particular, saturation magnetization rapidly decreases at thicknesses less than about 0.07 µm. From this perspective, it is concluded that a thickness larger than about 0.07 µm is available for practical use. For oxidation-annealed γ- Fe2O3 media, signal-output and media transition length are proportional to δ0.7 and δ0.5, respectively. A γ-(Co0.025Cu0.03Fe0.945)2O3 medium with a 0.071 µm thickness shows 0.51 mV of Epp, 2000 frpm of D-6 dB, -35 dB of O/W and 38 dB of SNR.