The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

This paper considers a test set for a multibit shifter which can execute arbitrary bit length shifting/rotating operations. The multibit shifter consists of several stages of sub-shifters, each of which can shift/rotate its inputs by an arbitrary number of bits less than or equal to a predetermined constant. Outputs of one sub-shifter are shifted/rotated in the next sub-shifted. All of the sub-shifters have the same structure, and are constructed with multiplexers. Every sub-shirter is separately tested. All of the multiplexers in each sub-shifter are tested in parallel and exhaustively. A minimum test set for every sub-shifter can be obtained by the use of an algorithm which generates a Boolean 2pq matrix M such that any 2pp submatrix of M includes all bit patterns of length p, where p and q (pq) are the numbers of input lines in a multiplexer and those in a sub-shifter, respectively. A complete test set for the multibit shifter can be easily obtained as the union of minimum test sets for all sub-shifters.

The locally exhaustive testing of multiple output combinational circuits is the test which provides exhaustive test patterns for each set of inputs on which each output depends. First, this paper presents a sufficient condition under which a minimum test set (MLTS) for the locally exhaustive testing has 2w test patterns, where w is the maximum number of inputs on which any output depends. Next, we clarify that any CUT with up to four outputs satisfies the condition, independently of w and n, where n is the number of inputs of the CUT. Finally, we clarify that any CUT with five outputs also satisfies the condition for 1w2 or n2wn.

Any minimum test set (MLTS) for locally exhaustive testing of multiple output combinational circuits (CUTs) has at least 2w test patterns, where w is the maximum number of inputs on which any output depends. In the previous researches, it is clarified that every CUT with up to four outputs has an MLTS with 2w elements. On the other hand, it can be easily shown that every CUT with more than five outputs does not have such an MLTS. It has not been however known whether every CUT with five outputs has such an MLTS or not. In this paper, it is clarified that every CUT with five outputs has such an MLTS. First, some terminologies are introduced as preliminaries. Second, features of 5(w1) dependence matrices of CUTs with five outputs and (w1) inputs are discussed. Third, an equivalence relation between dependence matrices of two CUTs is introduced. The relation means that if it holds and one of the CUTs has an MLTS with 2w elements, then the other CUT also has such an MLTS. Based on the features described above, a theorem is established that there exists a 5w dependence matrix which is equivalent to each of the above 5(w1) matrices. Finally, it is proved by the use of the theorem that every CUT with five outputs has an MLTS with 2 w elements.

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.

This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

A method to detect open node defects that cannot be detected by the conventional IDDQ test method has previously been proposed employing a sinusoidal wave superposed on the DC supply voltage. The present paper proposes a strategy to improve the detectability of the test method by means of frequency analysis of the supply current. In this strategy, defects are detected by determining whether secondary harmonics of the sinusoidal wave exist in the supply current. The effectiveness of the method is confirmed by experiments on two CMOS NAND gate packages (SSIs).