1-9hit |
Kenichi HORIGUCHI Atsushi OKAMURA Masatoshi NAKAYAMA Yukio IKEDA Tadashi TAKAGI Osami ISHIDA
Weight divided adaptive control method for a microwave FeedForward Power Amplifier (FFPA) is presented. In this adaptive controller, an output signal of a power amplifier is used as reference signal. Additionally, reference signal is divided by the weight of adaptive filter, so that characteristics of the power amplifier, such as temperature dependence, do not have influence on the convergence performances. The proposed adaptive algorithm and the convergence condition are derived analytically and we clarify that the proposed weight divided adaptive algorithm is more stable than the conventional Normalized Least Mean Square (NLMS) algorithm. Then, the convergence condition considering phase calibration error is discussed. The effectiveness of the proposed algorithm are also verified by the nonlinear simulations of the FFPA having AM-AM and AM-PM nonlinearity of GaAsFET.
Tadashi TAKAGI Satoshi OGURA Yukio IKEDA Noriharu SUEMATSU
A novel analysis method of the intermodulation (IM) and the noise power ratio (NPR) of multiple-carrier amplifiers is descrided. This method, based on Discrete Fourier Transform, allows an accurate calculation of IM and NPR of the amplifier having multiple carriers by directly using measured single-carrier amplitude and phase characteristics. This method has an outstanding feature in that it can be applied to the general case of n carriers having an arbitrary power level as long as frequency-dependence of amplitude and phase characteristics is negligibly small. Applying this method to the linearized amplifier, a good agreement between measured and calculated results for IM3, IM5, and NPR has been obtained for operation from linear up to saturation, which shows this method would be a good candidate for calculating IM and NPR of multiple-carrier amplifiers.
Kenichi HORIGUCHI Masatoshi NAKAYAMA Yuji SAKAI Kazuyuki TOTANI Haruyasu SENDA Yukio IKEDA Tadashi TAKAGI Osami ISHIDA
A high efficiency feedforward power amplifier (FFPA) with a series diode linearizer for cellular base stations is presented. In order to achieve the highest overall efficiency of an FFPA, an improved pre-distortion diode linearizer has been used and the bias condition of the main amplifier has been optimized. The optimum bias condition has been derived from the overall efficiency analysis of the FFPA with a pre-distortion linearizer. From measured overall performances of the FFPA, efficiency enhancement of the series diode linearizer has been verified. The developed FFPA achieved the efficiency of 10% and output power of 45.6 dBm at 10 MHz offset Adjacent Channel leakage Power Ratio (ACPR) -50 dBc under Wide-band Code-Division Multiple-Access (W-CDMA) modulated 2 carriers signal. This design method can be also used to optimize the source and load impedances condition of the main amplifier FET.
Hidenori YUKAWA Masatoshi NII Yoshihiro TSUKAHARA Yukio IKEDA Yasushi ITOH
A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.
Kenichi HORIGUCHI Kazuhisa YAMAUCHI Kazutomi MORI Masatoshi NAKAYAMA Yukio IKEDA Tadashi TAKAGI
This paper proposes a new distortion analysis method for frequency-dependent FET amplifiers, which uses a novel Frequency-Dependent Complex Power Series (FDCPS) model. This model consists of a frequency-independent nonlinear amplifier represented by an odd-order complex power series and frequency-dependent input and output filters. The in-band frequency characteristics of the saturation region are represented by the frequency-dependent output filter, while the in-band frequency characteristics of the linear region are represented by the frequency-dependent input and output filters. In this method, the time-domain analysis is carried out to calculate the frequency-independent nonlinear amplifier characteristics, and the frequency-domain analysis is applied to calculate the frequency-dependent input and output filter characteristics. The third-order intermodulation (IM3) calculated by this method for a GaAs MESFET amplifier is in good agreement with the numerical results obtained by the Harmonic Balance (HB) method. Moreover, the IM3 calculated by this method also agrees well with the measured data for an L-band 3-stage GaAs MESFET amplifier. It is shown that this method is effective for calculating frequency-dependent distortion of a nonlinear amplifier with broadband modulation signals.
Yukio IKEDA Kazutomi MORI Masatoshi NAKAYAMA Yasushi ITOH Osami ISHIDA Tadashi TAKAGI
An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.
Kazuhisa YAMAUCHI Masatoshi NAKAYAMA Yukio IKEDA Akira AKAISHI Osami ISHIDA Naoto KADOWAKI
An 18 GHz-band Microwave Monolithic Integrated Circuit (MMIC) diode linearizer using a parallel capacitor with a bias feed resistance is presented. The newly employed parallel capacitor is able to control gain and phase deviations of the linearizer. This implies that the gain deviation of the linearizer can be controlled without changing the phase deviation. The presented linearizer can compensate the distortion of an amplifier sufficiently. The operation principle of the linearizer with the parallel capacitor is investigated. It is clarified that the gain deviation can be adjusted without changing the phase deviation by using the parallel capacitor. Two variable gain buffer amplifiers and the core part of the linearizer which consists of a diode, a bias feed resistor, and a capacitor are fabricated on the MMIC chip. The amplifiers cancel the frequency dependence of the core part of the linearizer to improve bandwidth of the MMIC. Further, the amplifiers contribute to earn low reflection and compensate insertion loss of the linearizer. The MMIC chip is size of 2.5 mm 1 mm. The linearizer has demonstrated improvement of 3rd Inter-Modulation Distortion (IMD3) of 12 dB at 18 GHz and improvement of more than 6 dB between 17.8 GHz and 18.6 GHz.
Kazutomi MORI Kenichiro CHOUMEI Teruyuki SHIMURA Tadashi TAKAGI Yukio IKEDA Osami ISHIDA
A GSM900/DCS1800 dual-band AlGaAs/GaAs HBT (heterojunction bipolar transistor) MMIC (monolithic microwave integrated circuit) power amplifier has been developed. It includes power amplifiers for GSM900 and DCS1800, constant voltage bias circuits and a d. c. switch. In order to achieve high efficiency, the outside-base/center-via-hole layout is applied to the final-stage HBT of the MMIC amplifier. The layout can realize uniform output load impedance and thermal distribution of each HBT finger. The developed MMIC amplifier could provided output power of 34.5 dBm and power-added efficiency of 53.4% for GSM900, and output power of 32.0 dBm and power-added efficiency of 41.8% for DCS1800.
Yukio IKEDA Kazutomi MORI Shintaro SHINJO Fumimasa KITABAYASHI Akira OHTA Tadashi TAKAGI Osami ISHIDA
An L-Band high efficiency and low distortion multi-stage amplifier using self phase distortion compensation technique is presented. In this amplifier, the bias condition of the driver-stage transistor is tuned to compensate the phase distortion of the power-stage transistor, and the load and source impedances of the driver-stage and power-stage transistors are optimized to achieve the maximum efficiency with a specified adjacent channel leakage power (ACP) for multi-stage amplifier. The developed amplifier achieves a power added efficiency (Eadd) of 42.8% and an output power (Pout) of 26.8 dBm with an ACP of -38 dBc at 1.95 GHz for wide-band code-division multiple-access (W-CDMA) cellular phones.