Even though BiCMOS process has an ability to make both BJT and MOSFET on single-chip, only BJT has been used for BiCMOS Si-MMIC LNA because of its low noise and high gain performance under low d. c. supply power. But the distortion performance of BJT should be improved for the receiver applications in some wireless systems. In this paper, intermodulation distortion characteristics comparison is carried out between BJT and MOSFET fabricated in the same BiCMOS process by the analysis based on the simplified transistor models with extracted device parameters. The analytical result shows that MOSFET has lower intermodulation distortion characteristics compared with BJT, and the result is evaluated by the measurements. In order to obtain both low distortion and low noise characteristics, a two-stage Si-MMIC LNA is developed by using BJT as the 1st stage and MOSFET as the 2nd stage of LNA. The fabricated LNA performs NF of 2.45 dB, gain of 19.3 dB, IIP3 of14.6 dBm and OIP3 of 4.7 dBm under 3 V/7.2 mA d. c. supply power.

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

A C-Ku band 5-bit MMIC phase shifter using optimized reflective series/parallel LC circuits is presented. The proposed circuit has frequency independent characteristics in the case of 180 phase shift, ideally. Also, an ultra-broad-band circuit design theory for the 180 optimized reflective circuit has derived, which gives optimum characteristics compromising between loss and phase shift error. The fabricated 5-bit MMIC phase shifter with SPDT switch has successfully demonstrated a typical insertion loss of 9.4 dB 1.4 dB, and a maximum RMS phase shift error of 7 over the 6 to 18 GHz band. The measured results validate the proposed design theory of the phase shifter.

This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

Adaptive antenna is a promising to increase the spectral efficiency of mobile radio systems. We developed a compact, cost effective planar Butler Matrix as a beam forming network of a multi beam antenna. This circuit consists of a thin substrate that the conductor attaches to both sides, and two thick substrates that the ground conductor attaches to one side. In this circuit, coupling by crossover causes amplitude and phase error of the Butler Matrix. By narrowing the strip width of the crossover, crossover coupling can be suppressed 10 dB. The measurement results of the experimental 88 Butler Matrix were 0.75 dB amplitude deviation, 9.5 degree phase deviation and VSWR of less than 1.15 within the relative bandwidth of 10% at 900 MHz band.

This letter describes a novel coupled-transmission-line directional coupler using an asymmetrical suspended stripline with unequal conducting strips on both sides of a dielectric substrate. The directional coupler has a rang of coupling values from 5 to 9 dB which is difficult to be realized by a conventional symmetrical suspended stripline coupler.

A high efficiency feedforward power amplifier (FFPA) with a series diode linearizer for cellular base stations is presented. In order to achieve the highest overall efficiency of an FFPA, an improved pre-distortion diode linearizer has been used and the bias condition of the main amplifier has been optimized. The optimum bias condition has been derived from the overall efficiency analysis of the FFPA with a pre-distortion linearizer. From measured overall performances of the FFPA, efficiency enhancement of the series diode linearizer has been verified. The developed FFPA achieved the efficiency of 10% and output power of 45.6 dBm at 10 MHz offset Adjacent Channel leakage Power Ratio (ACPR) -50 dBc under Wide-band Code-Division Multiple-Access (W-CDMA) modulated 2 carriers signal. This design method can be also used to optimize the source and load impedances condition of the main amplifier FET.

An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.

An 18 GHz-band Microwave Monolithic Integrated Circuit (MMIC) diode linearizer using a parallel capacitor with a bias feed resistance is presented. The newly employed parallel capacitor is able to control gain and phase deviations of the linearizer. This implies that the gain deviation of the linearizer can be controlled without changing the phase deviation. The presented linearizer can compensate the distortion of an amplifier sufficiently. The operation principle of the linearizer with the parallel capacitor is investigated. It is clarified that the gain deviation can be adjusted without changing the phase deviation by using the parallel capacitor. Two variable gain buffer amplifiers and the core part of the linearizer which consists of a diode, a bias feed resistor, and a capacitor are fabricated on the MMIC chip. The amplifiers cancel the frequency dependence of the core part of the linearizer to improve bandwidth of the MMIC. Further, the amplifiers contribute to earn low reflection and compensate insertion loss of the linearizer. The MMIC chip is size of 2.5 mm 1 mm. The linearizer has demonstrated improvement of 3rd Inter-Modulation Distortion (IMD3) of 12 dB at 18 GHz and improvement of more than 6 dB between 17.8 GHz and 18.6 GHz.

A compact Ku-band 5-bit monolithic microwave integrated circuit (MMIC) phase shifter has been demonstrated. The total gate width of switching FETs and the total inductance of spiral inductors are proposed as the figures of merit for compactness. The phase shifter uses the T-type and PI-type high-pass filter (HPF)/band-pass filter (BPF) circuits in which FET "off"-state capacitances are incorporated as the filter elements. According to the figures of merit, the T-type is selected for 90-degree phase shift circuit and the PI-type is selected for the 45-degree phase shift circuit. The fabricated 5-bit phase shifter performs average insertion loss of 5.6 dB and RMS phase shift error of 3.77 degrees with die size of 1.65 mm 0.76 mm (1.25 mm2) in Ku-band.

This paper describes the distortion characteristics of an even harmonic type direct converter (EH-DC) used in earth stations for CDMA satellite communications. Direct conversion technique is known as a method to simplify circuit topologies of microwave transceivers. In satellite communications, multi carriers which have high and nearly equal level are provided to a quadrature mixer of the EH-DC. Hence, the third-order intermodulation degrades receiving characteristics. In this paper, we show the relationship between the distortion characteristics and noise figure of the EH-DC for CDMA satellite communication systems. Furthermore, we show NPR of even harmonic quadrature mixers caused by the third-order intermodulation. Experimental results in X-band indicate that the proposed EH-DC has almost the same BER characteristics compared with a heterodyne type transceiver.

A GSM900/DCS1800 dual-band AlGaAs/GaAs HBT (heterojunction bipolar transistor) MMIC (monolithic microwave integrated circuit) power amplifier has been developed. It includes power amplifiers for GSM900 and DCS1800, constant voltage bias circuits and a d. c. switch. In order to achieve high efficiency, the outside-base/center-via-hole layout is applied to the final-stage HBT of the MMIC amplifier. The layout can realize uniform output load impedance and thermal distribution of each HBT finger. The developed MMIC amplifier could provided output power of 34.5 dBm and power-added efficiency of 53.4% for GSM900, and output power of 32.0 dBm and power-added efficiency of 41.8% for DCS1800.

An L-Band high efficiency and low distortion multi-stage amplifier using self phase distortion compensation technique is presented. In this amplifier, the bias condition of the driver-stage transistor is tuned to compensate the phase distortion of the power-stage transistor, and the load and source impedances of the driver-stage and power-stage transistors are optimized to achieve the maximum efficiency with a specified adjacent channel leakage power (ACP) for multi-stage amplifier. The developed amplifier achieves a power added efficiency (Eadd) of 42.8% and an output power (Pout) of 26.8 dBm with an ACP of -38 dBc at 1.95 GHz for wide-band code-division multiple-access (W-CDMA) cellular phones.

A low-loss serial power combiner using suspended stripline is described. It consists of novel broadside-coupled directional couplers which have shunt capacitances at the edges of the coupled sections. These additional shunt capacitances compensate for poor directivities of the couplers because of inhomogeneous dielectric in suspended stripline structure. The fabricated three-way power combiner has achieved good performance with insertion loss less than 0.23 dB over a bandwidth of 10% in 2 GHz band.

Weight divided adaptive control method for a microwave FeedForward Power Amplifier (FFPA) is presented. In this adaptive controller, an output signal of a power amplifier is used as reference signal. Additionally, reference signal is divided by the weight of adaptive filter, so that characteristics of the power amplifier, such as temperature dependence, do not have influence on the convergence performances. The proposed adaptive algorithm and the convergence condition are derived analytically and we clarify that the proposed weight divided adaptive algorithm is more stable than the conventional Normalized Least Mean Square (NLMS) algorithm. Then, the convergence condition considering phase calibration error is discussed. The effectiveness of the proposed algorithm are also verified by the nonlinear simulations of the FFPA having AM-AM and AM-PM nonlinearity of GaAsFET.