We present an extension of the previously proposed 3-layer feedforward network called a cascaded network. Cascaded networks are trained to realize category classification employing binary input vectors and locally represented binary target output vectors. To realize a nonlinearly separable task the extended cascaded network presented here is consreucted by introducing high order cross producted inputs at the input layer. In the construction of the cascaded network, two 2-layer networks are first trained independently by delta rule and then cascaded. After cascading, the intermediate layer can be understood as a hidden layer which is trained to attain preassigned saturated outputs in response to the training set. In a cascaded network trained to categorize binary image patterns, saturation of hidden outputs reduces the effect of corrupted disturbances presented in the input. We demonstrated that the extended cascaded network was able to realize a nonlinearly separable task and yielded better generalization ability than the Backpropagation network.

A global routing problem is formulated as a multi-commodity network flow problem. The formulation gives no restriction over the shape of a routing pattern and makes it possible to obtain the optimal solution by using a mathematical programming method. Moreover, it can be naturally extended to the problem even optimizing routing length objectives for net delay and clock skew perfomances by using the goal programming method. An approximation algorithm solving the multi-commodity network flow problem is proposed by adding a merge step of wires whose source-sink pairs are exactly the same and a step restricting an area for searching routes. Experimental results show that this global routing algorithm connected with a line-search detailed router can generate a complete routing for interblock routing problems with more than 2400 wires in two industrial chips. The total amount of procassing time for both problems is about 90 minutes on a mainframe computer.

The performance of ASIPs (Application Specific Integrated Processors) is heavily affected by the design of their instruction set architecture. In order to maximize the performance of ASIP, it is essential to design an architecture that has an optimum instruction set. This paper descibes a new method that automates the design of optimum instruction set of ASIP. This method solves the Instruction set implementation Method Selection Problem(IMSP). IMSP is to be solved in the instruction set architecture design. Frse, the IMSP is formalized as an integer programming problem, which is to maximize the perfomance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. The presented method automates a complex part of the ASIP chip design and is also a good design tool that enables designer to predict the performance of their design before completion.

We present algorithms for the optimization of sequential synchronous digital circuits using structural model, i.e. interconnections of combinational logic gates and synchronous registers. This approach contrasts traditional methods using state diagrams or transition tables and leveraging state minimization and encoding techniques. In particular, we model circuits by synchronous logic networks, that are weighted multigraphs representing interconnections of gates implementing scalar combinational functions. With this modeling style, area and path delays are explicit and their variation is easy to compute when circuit transformations are applied. Sequential logic optimization may target cycle-time or area minimization, possibly under area or cycle-time constraints. Optimization is performed by a sequence of transformations, directed to the desired goal. This paper describes the fundamental mechansms for transformations applicable to sequential circuits. We review first retiming and peripheral retiming techniques. The former method optimizes the position of the registers, while the latter repositions the registers to enlarge maximally the combinational region where combinational restructuring algorithms can be applied. We consider then synchronous algebraic and Boolean transformations, that blend combinational transformations with local retiming. Both classes of transformations require the representation of circuits by means of logic expressions with labeled variables, the labels representing discrete time-points. Algebraic transformations entail manipulation of time-labeled expressions with algebraic techniques. Boolean transformations exploit the properties of Boolean algebra and benefit from the knowledge of don't care conditions in the search for the best implementation of local functions. Expressing don't care conditions for sequential circuits is harder than for combinational circuits, because of the interaction of variables with different time labels. In addition, the feasibility of replacing a local function with another one may not always be verified by checking for the inclusion of the induced perturbation in local explicit don't care set. Indeed, the behavior of sequential circuits, that can be described appropriately by the relation between input and output traces, may require relational models to express don't care conditions. We describe a general formalism for sequential optimization by Boolean transformations, where the don't care conditions are expressed implicitly by synchronous recurrence equations. We present then an optimization method for this model, that can exploit degrees of freedom in optimization not possible for other methods, and hence providing solutions of possible superior quality. We conclude by summarizing the major features and limitations of optimization methods using structural models.

To clarify the stereopsis disturbance in patients with Alzheimer's disease (AD), we analyzed binocular eye movement when subjects shifted their gaze between targets at different depths. Subjects are patients with Alzheimer's disease, Mluti-infarct dementia (MID), or Olivopontocerebellar atrophy (OPCA), and healthy controls. Targets are arranged in two ways: along the median plane and asymmetrically crossing the median plane, at distances from the eyes of 1000 mm and 300 mm. When the targets are switched at the onset of a beep, the subjects shifted their gaze to the lit target. The experiment is conducted in a dimly lit room whose structure is capable of providing good binocular cues for depth. In AD subjects, especially in the subjects whose symptoms are moderate (advanced stage), vergence is limited and the change in the convergence angle is small, unstable, and non-uniform. These results are different from those of other patients (MID) and OPCA) or healthy controls and suggest a disturbance of stereopsis in the parietal lobe where AD patients typically have dysfunctions.

A shift down of the resonance frequency is claimed to be used as a simple practical test for the onset of chaos based on a common feature of forced damped nonlinear oscillation systems which exhibit cascading bifurcations to chaos.

It has been reported that generalization performance of multilayer feedformard networks strongly depends on the attainment of saturated hidden outputs in response to the training set. Usually standard Backpropagation (BP) network mostly uses intermediate values of hidden units as the internal representation of the training patterns. In this letter, we propose construction of a 3-layer cascaded network in which two 2-layer networks are first trained independently by delta rule and then cascaded. After cascading, the intermediate layer can be viewed as hidden layer which is trained to attain preassigned saturated outputs in response to the training set. This network is particularly easier to construct for linearly separable training set, and can also be constructed for nonlinearly separable tasks by using higher order inputs at the input layer or by assigning proper codes at the intermediate layer which can be obtained from a trained Fahlman and Lebiere's network. Simulation results show that, at least, when the training set is linearly separable, use of the proposed cascaded network significantly enhances the generalization performance compared to BP network, and also maintains high generalization ability for nonlinearly separable training set. Performance of cascaded network depending on the preassigned codes at the intermediate layer is discussed and a suggestion about the preassigned coding is presented.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

The objective of this work is to demonstrate a new hierarchical timing analysis technique for multi-phase clocked designs with feedback loops including level sensitive latches. By using this technique, large synchronous designs can be analyzed accurately without loop breaking.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

We propose a hierarchical multi-layer global router for Sea-Of-Gates VLSI's, which is different from the conventional global routers, in that routing and layering are executed simultaneously. The main problems to be solved in the global routing for a multi-layer VLSI are which wire segments are laid out on upper layers and how they are connected to terminals located on lower layers. The main objective is to minimize the maximum of local congestions of all layers. We solve these problems in a hierarchical manner by routing from upper layers to lower layers.

An integrated CAD/CAM system for MMIC development has been firstly realized, which consists of electron beam direct drawing, microwave circuit simulator, pattern generator and RF &DC on-wafer automatic measurement subsystems, connected through an Ethernet LAN. The system can develop not only new MMICs and their element devices, but also their accurate simulation models quickly and efficiently. Preliminary successful applications of this system have been demonstrated by DC-HFET with a 0.25 µm T-shaped gate electrode and MMIC low-noise amplifiers operating at X- and L-bands.

A new model for a computer simulation of RF capacitive type hyperthermia has been developed by taking account of the following points. Blood flow is usually determined by many physiological parameters, but is regarded as a function of only blood temperature under some conditions. The temperature dependence of blood flow of tumors and normal tissues is assumed by referring the data obtained by Song et al. and Tanaka. The blood temperature which is elevated by externally applied power significantly affects temperatures of the body and the tumors. The transport of heat from the body surface is studied by considering air convection. These points are examined by experiments on a computer with simple phantom models and real patients. The results of simulation on the patient have shown a good agreement with clinical inspection based on CT images and a temperature of the stomach.

In this paper, a "hydrodynamic" version of the three-dimensional code HFIELDS-3D is used to achieve a detailed knowledge on the distribution of the substrate current inside a recessed-oxide MOSFET. The physical model features a temperature-dependent formulation of the impact-ionization rate, allowing non-local effects to be accounted for. The discretization strategy relies on the Box Integration scheme and uses suitable generalizations of the Scharfetter-Gummel technique for the energy-balance equation. The simulation results show that the narrow-channel effect has a different impact on drain and substrate currents. Further three-dimensional effects, such as the extra heating of the carriers at the channel edge, are demonstrated.

A spherical-harmonics expansion method is used to find approximate numerical solutions of the Boltzmann Transport Equation in the homogeneous case. Acoustic and optical phonon scattering, ionized impurity scattering as well as an energy band structure fitting the silicon density of states up to 2.6 eV above the conduction-band edge are used in the model. Comparisons with Monte Carlo data show excellent agreement, and prove that detailed information on the high-energy tail of the distribution function can be obtained at very low cost using this methodology.

In this paper, we propose a new algorithm for the problem of floorplanning of the mixed design of macro and standard cells. The proposed algorithm which is based on partitioning and slicing approach, uses a modified min-cut bipartitioning heuristic. The heuristic bipartitions a block of a mixture of macro and standard cells to minimize the netcut, which are the number of nets connecting both sub-blocks, with size constraints. A sub-block is a resulting descendant block. Before starting the bipartitioning of the block, the macro cell with the longest side in the block is selected first. Using edges of the selected macro cell, bipartitionings are performed twice fixing the location of the macro cell on one of 4 corners of the block with its rotation and reflection. Bipartitioning of blocks is repeated until each block has either a macro cell or standard cells without macro cells. As a result of bipartitioning, a slicing tree is constructed. Using the proposed floorplan algorithm, we developed an automatic placement and routing tool, Cell Designer, for the mixed design of macro and standard cells. According to the floorplanner, macro cells are placed and standard cells are grouped into standard cell blocks. Standard cells are placed and routed within estimated area of block using conventional tools. They form a fixed-shaped block like a macro cell. Interconnections between the two adjacent blocks are performed with a conventional channel router. The channels and the order of channel routing are determined following the hierarchy of the slicing tree. Cell Designer has a dedicated graphics editor to provide interactive services to users. Experimental results on well-known benchmark data are shown.

An automatic optimization system for semiconductor devices has been built-up by fully interfacing an optimizer and a device-analysis code supplemented with sensitivity analysis. The device-analysis code is thought of as a part of a pipeline of simulators. The latters are regarded as subprocesses by the optimizer, which controls their I/O stream. The action of the pipeline is iterated until the optimum set of design parameters is determined. An important feature of the system is that all the derivatives required in the sensitivity analysis are calculated analytically, this providing a substantial improvement in both the numerical accuracy and computational efficiency, and making the scheme attractive from the application standpoint. A few examples of optimization of MOS devices are shown and the performance is reported, indicating that a system of this kind can usefully be exploited in a design environment.