The analytic expression for the transmission spectrum of cascaded long-period fiber gratings is presented in a closed form. When several identical gratings are cascaded in-series with a regular distance, the transmission spectrum is revealed to have a series of regularly spaced peaks, suitable for multi-channel filters. The analytic solution is obtained by diagonalizing the transfer matrix of each grating unit that is composed of a single grating and a grating-free region between adjacent gratings. The spectrum of the device is simply described with the number of cascaded gratings and a single parameter that has the information of the phase difference between the modes. With the derived equation, the spectral behaviors of the proposed device are investigated. The intensity of each peak can be controlled by adjusting the strength of a single grating. The separation between adjacent gratings determines the spacing between the peaks. The finesse of the peaks can be increased by cascading more gratings. The derived analytic results are compared with the known results of paired gratings and phase-shifted gratings.

Wire delays, instead of gate delays, are moving into dominance in modern VLSI design. Current synchronous processors have the critical path not in the ALU function but in the cache access. Since the cache performance enhancement is limited by the memory access delay which mainly consists of wire delays, a reduction in gate delays may no longer imply any enhancement in processor performance. To solve this problem, this paper presents a novel architecture, called the Cascade ALU. The Cascade ALU allows super-scalar processors with future technologies to move the critical path into the ALU part. Therefore the Cascade ALU can enjoy the expected progress in future device speed. Since the delay of the Cascade ALU varies depending on the executed instructions, an asynchronous system is shown to be suitable for implementing the Cascade ALU. However an asynchronous system may have a large handshake overhead, this paper also presents an asynchronous Fine Grain Pipeline technique that hides the handshake overhead. Finally, this paper presents results of performance and area evaluation for an asynchronous implementation of the cascade ALU. The results show that the cascade ALU architecture has a good performance scalability on the reduction of the ALU latency and imposes little area penalty compared with current synchronous processors.

A known problem of the four-phase handshaking protocol is that a return-to-zero phase of the signals involved in the handshake is necessary before starting another cycle, in which no useful work is usually done. In this paper we first define an easy-to-write specification style to specify four-phase handshaking asynchronous controllers that can be translated to an STG to obtain a gate-level implementation using existing synthesis methods. Then, we propose an algorithm that takes the specification written using our specification style and finds an optimized timing in which the idle-phase overhead of its gate-level implementation is reduced.

This paper newly proposes radio-over-fiber systems using cascaded radio-to-optic direct conversion (ROC) scheme. The ROC system can convert a radio signal into an optical signal with the same signal format. The received carrier-to-noise ratio (CNR) performance of the radio-over-fiber systems using the ROC/heterodyne detection (HD) scheme and the ROC/self-heterodyne detection (SHD) scheme are theoretically analyzed. The optimization of an optical modulation index (OMI) in each radio base station (RBS) is also presented. By using the proposed OMI optimization method, the ROC/HD and the ROC/SHD schemes are shown to provide approximately 16 dB and 14 dB improvement over the intensity modulation/direct detection scheme when the number of RBS is 20 and the radio-frequency (RF) signal bandwidth is 150 MHz, respectively. The ROC/SHD scheme enables a receiver structure to become simple while still achieving high received CNR.

The application of Technology CAD simulations for development of IC processes in foundry is presented. Examples include device design, Flash cell design and optical proximity correction for SRAM cell. The challenges of using TCAD tools in the IC foundry is also discussed.

We propose a new active vision system that mimics a saccadic movement of human eye. It is implemented based on a new computational model using neural networks. In this model, the visual pathway was divided in order to categorize a saccadic eye movement into three parts, each of which was then individually modeled using different neural networks to reflect a principal functionality of brain structures related with the saccadic eye movement in our brain. Initially, the visual cortex for saccadic eye movements was modeled using a self-organizing feature map, then a modified learning vector quantization network was applied to imitate the activity of the superior colliculus relative to a visual stimulus. In addition, a multilayer recurrent neural network, which is learned by an evolutionary computation algorithm, was used to model the visual pathway from the superior colliculus to the oculomotor neurons. Results from a computer simulation show that the proposed computational model is effective in mimicking the human eye movements during a saccade. Based on the proposed model, an active vision system using a CCD type camera and motor system was developed and demonstrated with experimental results.

This paper proposes a reference model of CAD system generation, and describes its prototype implementation. The problems encountered in using CAD systems in industry involve complicated data handling and unsatisfied demands for domain knowledge because of the lack of a way of extracting and adopting it in the system. In the example domain of architecture, the authors have already defined domain-specific BDL (Building Design Language) for architecture experts to describe modelers of architectural structure in CAD systems by themselves. Moreover, the authors have developed a CAD system generator based on BDL descriptions. However, the different domain-specific languages required for individual domains create difficulty in developing various CAD system generators. The proposed reference model solves this problem by applying a common intermediate language based on the object model. Moreover, the model allows the creation of an integrated CAD system which contains multiple domains required by a field of industry. Its prototype implementation demonstrates its feasibility.

A novel temperature sensor device based on a conventional long-period fiber grating but having an improved sensing resolution is presented. By forming a reflector at one cleaved end of the fiber embedding a long-period grating, a fine interference fringe pattern was obtained within the conventional broadband resonant spectrum of the grating. Due to the fine internal structure of the reflection spectrum of the proposed device, the accuracy in reading the temperature-induced resonant wavelength shift was improved. The formation of the self-interference fringe is analyzed and its properties are discussed in detail. The performance of the proposed device is analyzed by measuring the resonant wavelength shift of the device placed in a hot oven under varying temperature. The rate of the fringe shift is measured to be 551 pm/. The rms deviation is 10 pm over a 100 dynamic range, which corresponds to 0.2 in rms temperature deviation. The thermal variation of the differential effective index of the fiber is calculated to be (0.3 0.1)10-6/ by comparing the analytic calculations with the experimental results. The interference fringe shift is revealed to be inversely proportional to the differential effective group index of the fiber, which implies that the shifting rate strongly depends on the type of fibers and also on the order of the involved cladding mode.

Fully automatic reconstruction of 3D models from images is well-known to be a difficult problem. For many applications, a limited amount of human assistance is allowed and can greatly reduce the complexity of the 3D reconstruction problem. In this paper, we present an easy-to-use method for aligning a parameterized 3D CAD model to images taken from different views. The shape parameters of the 3D CAD model can be recovered accurately. Our work is composed of two parts. In the first part, we developed an interactive tool which allows the user to associate the features in the CAD model to the features in the 2D images. This interactive tool is designed to achieve efficiency and accuracy. In the second part, 3D information extracted from different stereo views are integrated together by using an optimization technique to obtain accurate shape parameters. Some experimental results have been shown to demonstrate the accuracy and usefulness of the recovered CAD model.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.

Clustering is almost essential in improving the performance of iterative partitioning algorithms. In this paper, we present a clustering algorithm based on the following observation: if a group of cells is assigned to the same partition in numerous local optimum solutions, it is desirable to merge the group into a cluster. The proposed algorithm finds such a group of cells from randomly generated local optimum solutions and merges it into a cluster. We implemented a multilevel bipartitioning algorithm (MBP) based on the proposed clustering algorithm. For MCNC benchmark netlists, MBP improves the total average cut size by 9% and the total best cut size by 3-4%, compared with the previous state-of-the-art partitioners.

TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size, with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very large circuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.

This paper presents a new routing method that takes into account neighboring-wire-capacitance (inter-layer and intra-layer) constraints. Intermediate routing (IR) assigns each H/V wire segment to the detailed routing (DR) grid using global routing (GR) results, considering the neighboring-wire constraints (NWC) for critical nets. In DR, the results of IR for constrained nets and their neighboring wires are preserved, and violations that occur in IR are corrected. A simple method for setting NWC that satisfy the initial wire capacitance given in a set-wire-load (SWL) file is also presented. The routing method enables more accurate delay evaluation by considering inter-wire capacitance before DR, and avoids long and costly turnaround in deepsubmicron layout design. Experimental results using MCNC benchmark test data shows that the errors between the maximum delay from IR and that from DR for each net were less than 5% for long (long delay) nets.

An extended desktop multimedia conference system named FREDERIC (File Retrieval Engineering on Distributed EnviRonment and Interactive Communication system) has been developed for international cooperative work by sharing CAD and image data among multi-point users. This paper describes the basic network design concept of utilizing the Internet as a best-effort service and ISDN as a high-speed guaranteed service. Service system requirements and designs were developed to access common databases and collaborative work of multimedia information those are shared by customers with desktop computers and to allow remote offices to use a plant walkthrough system. The performance of the prototype system especially focused on the file transmission time which is the key factor in developing and constructing the system. By applying the image compression technology of multi-tone entropy coding, it is shown that the short time CAD data transfer to meet the requirements can be achieved.

A novel method for the guided-probe diagnosis of high-performance LSIs containing macrocells, which have no internal netlist essential to the diagnosis, has been developed. In this method, the macrocell netlist is derived from its layout by extracting a leaf-cell-level netlist and is combined with the original one. Logic models for the leaf cells in the extracted netlist are also generated to obtain the logic-simulation data in the macrocells. The logic modeling is extended for application to memory macrocells, based on the idea that analog-behavior leaf cells in the memory macrocells are converted into logically equivalent circuits for logic simulation. Specifically, sense amplifiers and wired-or connections on bit lines are replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual design data of LSIs containing macrocells, and it has been verified that it enables fault paths inside macrocells to be accurately traced and that the logic models give good timing resolution in the logic simulation. Using the proposed method, LSIs containing macrocells will be able to be diagnosed regardless of the macrocell types, without the need for a "golden" device, by an electron-beam guided probe system.