A tri-band Multiple-input-multiple-output (MIMO) antenna system for LTE 700, LTE2500 and GSM 1800/1900 mobile handset application is presented. The whole system consists of four identical 3-D IFAs (inverted F antenna) folded on FR4 cuboids. Without any special designed decoupling structures, the measured isolation among antenna elements is higher than 20dB in the low and upper bands, even in the middle band, the isolation is higher than 13.7dB. Reflection coefficient, correlation coefficient, gain and radiation pattern are also presented. Acceptable agreement between the antenna models with and without plastic housing, battery and LCD screen demonstrate that the proposed antenna is a competitive candidate for mobile handsets.

In this paper, we design a stealthy GSM phone identity catcher. As the GSM protocols do not mandate the authentication of BSes (Base Stations) to MSes (Mobile Stations), fake BSes can be implemented to lure victims to register with and thereby intercept crucial information of the user, including their identities. However, the straightforward implementation of GSM phone identity catcher can be easily perceived by users employing detection software due to such phenomena as phone interface changes and service interruptions. In this paper, we propose several effective mechanisms, such as smart configuration of the fake BSes, quick attachment/detachment and service relay, to make the catching process invisible to users and software. Real world experiments have been conducted and the results prove the efficiency and stealth of our proposed GSM phone identity catcher. We hope our work could help to enhance the effectiveness of IMSI catching attack and thereby alert the industry to design stronger authentication protocol in communication systems.

In this letter, we learned overcomplete filters to model rich priors of nature images. Our approach extends the Gaussian Scale Mixture Fields of Experts (GSM FOE), which is a fast approximate model based on Fields of Experts (FOE). In these previous image prior model, the overcomplete case is not considered because of the heavy computation. We introduce the assumption of quasi-orthogonality to the GSM FOE, which allows us to learn overcomplete filters of nature images fast and efficiently. Simulations show these obtained overcomplete filters have properties similar with those of Fields of Experts', and denoising experiments also show the superiority of our model.

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

The linearity and noise required by GSM and UMTS receivers make the design of a CMOS mixer for these applications so challenging. A new technique for IP2 improvement in Zero-IF active mixers is presented in this paper. This inductor-less technique is based on canceling the parasitic capacitor of common source node of the switching transistors and synthesizing resistive impedance. Using this technique, a reconfigurable down converter mixer works from 900 MHz to 2.4 GHz is designed supporting GSM, DCS, PCS, UMTS and IEEE802.11 b-g standards. The mixer IIP2 is higher than 71 dBm in GSM and UMTS bands. The mixer conversion gain is higher that 12 dB in all frequency bands. The design is done in 65 nm CMOS technology and consumes 10 mA from a 1.2 V supply. The design meets the performance required for all mentioned standards, while its area and power is comparable with high performance single band mixers.

This paper describes a 3.5 V operation InGaP HBT MMIC power amplifier module for use in GSM/EDGE dual-mode, 900/1800/1900 MHz triple band handset applications. Conventional GSM amplifiers have a high linear gain of 40 dB or more to realize efficiency operation in large gain compression state exceeding at least 5 dB. On the other hand, an EDGE amplifier needs a linear operation to prevent signal distortion. This means that a high linear gain amplifier cannot be applied to the EDGE amplifier, because the high gain leads to the high noise power in the receive band (Rx-noise). In order to solve this problem, we have changed the linear gain of the amplifier between GSM and EDGE mode. In EDGE mode, the stage number of the amplifier changes from three to two. To reduce a high gain, the first stage transistors in the amplifier is bypassed through the diode switches. This newly proposed bypass circuit enables a high gain in GSM mode and a low gain in EDGE, thus allowing the amplifier to operate with high efficiency in both modes while satisfying the Rx-noise specification. In conclusion, with diode switches and a band select switch built on the MMIC, the module delivers a Pout of 35.5 dBm and a PAE of about 50% for GSM900, a 33.4 dBm Pout and a 45% PAE for GSM1800/1900. While satisfying an error vector magnitude (EVM) of less than 4% and a receive-band noise power of less than -85 dBm/100 kHz, the module also delivers a 29.5 dBm Pout and a PAE of over 25% for EDGE900, a 28.5 dBm Pout and a PAE of over 25% for EDGE1800/1900.

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented in this paper. This chip uses low-IF and zero-IF receiver architectures for GSM and WCDMA respectively to fulfill the entirely different system requirements of the two standards. It consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end is implemented in a standard 0.25 µm CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3 dB, 36 dB for the GSM900, 5.9 dB, 31 dB for the DCS1800, and 4.3 dB, 29.6 dB for the WCDMA, respectively.

This letter describes a dual band planar inverted-F antenna (PIFA) with non-uniform meander-line shaped slot suitable for the mobile environment scenario, which operates at the GSM 900 MHz and GSM 1800 MHz (DCS) bands. This antenna structure overcomes the lack of height of the mobile phone. In a practical mobile handset, the bandwidths of the antenna for return loss -8.5 dB are 240 MHz at 900 MHz and 250 MHz at 1800 MHz. Good impedance bandwidth performance for the dual-band is observed. The advantage of the design suggested in this letter is its simplicity of manufacturing and low cost.

This work presents a new sigma-delta modulator (SDM) architecture for a wide bandwidth receiver. This architecture contains dual-bandwidth for W-CDMA and GSM system applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used together. Using the low-distortion swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM extends the signal bandwidth and represses the high-band noise. The SDM used in the W-CDMA and GSM applications was designed and simulated using 0.25-µm 1P5M CMOS technology. The simulated peak SNDR of W-CDMA and GSM are 72/70 dB and 82/84 dB in Low-IF/Zero-IF standards.

The architecture and implementation of a novel processor suitable wireless terminal applications, is introduced. The wireless terminal is based on the novel dual-mode baseband processor for DECT and GSM, which supports both heterodyne and direct conversion terminal architectures and is capable to undertake all baseband signal processing, and an innovative direct conversion low power modulator/demodulator for DECT and GSM. The state of the art design methodologies for embedded applications and innovative low-power design steps followed for a single chip solution. The performance of the implemented dual mode direct conversion wireless terminal was tested and measured for compliance to the standards. The developed innovative terminal fulfils all the requirements and specifications imposed by the DECT and GSM standards.

A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.

A new type of triple-band antenna is introduced by combing a tab monopole antenna (TMA) and a planar inverted F antenna (PIFA). The antenna configuration is shown to operate at three discrete frequencies: GSM 900, GSM 1800 (DCS) and GSM 1900 (PCS). The performance of an antenna is presented as well as the results of the computer simulations with a software package based on the Finite Element Method. The simulated results with the real antenna's experimental results. The advantage of the design suggested in this paper is its simplicity of manufacturing and low cost.

A highly efficient power MOSFET has been developed for 3.6 V RF power amplifiers for use in GSM (Global Systems for Mobile communications) cellular telephone systems (880-915 MHz). It was fabricated using a 0.45-µm CMOS LSI process with an Al-shorted metal-silicide/Si gate structure instead of a conventional 0.8-µm Mo-gate. The resulting power MOSFET has an on-state resistance of 6.9 Ωmm, a breakdown voltage of 13 V, and a cut-off frequency of 11 GHz. The RF performance of the device achieved an output power (Pout) of 1.8 W, a power gain of 10 dB, and a power-added efficiency (ηadd) of 60%. In addition, an RF power module using our proposed power MOSFET achieved an output power of 4 W and a total efficiency of 50%.

This paper describes a 270-MHz CMOS quadrature modulator (QMOD) for a global system for mobile communications (GSM) transmitter. QMOD consists of two attenuators and two doubly-balanced modulators (DBM's) and fabricated by using 0.35-µm CMOS process. The carrier leakage level of -35.7 dBc and the image rejection level of -45.1 dBc are achieved. It's total chip area is 880 µm550 µm and it consumes 1.0 mA with 3.0 V power supply.

The General Packet Radio Service (GPRS) is a new bearer service for GSM that greatly improves and simplifies wireless access to packet data networks, e.g., to the Internet. It applies a packet radio principle to transfer user data packets in an efficient way between mobile stations and external packet data networks. This tutorial gives an introduction to GPRS. The article discusses the system architecture and its basic functionality. It explains the offered services, the session and mobility management, the routing, the GPRS air interface including channel coding, and the GPRS protocol architecture. Finally, an interworking example between GPRS and IP networks is shown.

This paper describes a CMOS Offset Phase Locked Loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of -163.5 dBc/Hz, the phase error of 0.66rms, and the settling time of 40µs were achieved. The IC was implemented by using 0.35-µm CMOS process. It takes 860µm620µm of total chip area and consumes 17.6 mA with a 3.0 V power supply.

This paper presents the subjective speech quality evaluation in terms of the Mean Opinion Score (MOS) and the relationship between BER and subjective speech quality in a GSM-based radio system. The results show that in certain environments (hilly terrain and rural areas), a SNR (or C/I) higher than 12 dB is required for acceptable speech quality. For an acceptable speech quality, a BER(c1) better than 10-2 is needed in a GSM-based system.

A new GSM data protocol called high speed circuit switched data (HSCSD) have been developed by European Telecommunications Standards Institute (ETSI) for high speed file transfer and mobile video applications. HSCSD increases data rate by using multiple TDMA time slots (up to 8) instead of one time slot in the current GSM implementation. The problem of multiple time slot assignment is that blocking rate of the system will increase. This problem can be solved by flexible resource assignment where the service specifies the maximum and the minimum capacity. Based on the current available capacity of a base station, a user will be assigned any rate between the maximum and the minimum capacities. This article describes HSCSD protocol and presents four radio resource allocation strategies for HSCSD: always allocates maximum, always allocates minimum, allocates maximum unless available resources are not enough, and allocates resources according to the current blocking statistics of the base station. A simulation model is proposed to investigate the performance of these algorithms. The blocking probability, the call completion probability, and the quality of service are used to evaluate the effects of algorithms in different system behaviors.

A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.