The relay channel is the common approach to cooperative communication. Quasi-cyclic low-density parity-check (QC-LDPC) code design for the relay channel is important to cooperative communication. This paper proposes a bilayer QC-LDPC code design scheme for the relay channel. Combined with the bilayer graphical code structure, an improved Chinese remainder theorem (CRT) method, the Biff-CRT method is presented. For the proposed method we introduce a finite field approach. The good performance of the finite field based QC-LDPC code can improve the performance of its corresponding objective QC-LDPC code in the proposed scheme. We construct the FF code and the FA code by the Biff-CRT method. The FF code and the FA code are both named as their two component codes. For the FF code, the two component code are both finite field based QC-LDPC codes. For the FA code, one of the component codes is the finite field based QC-LDPC code and the other is the array code. For the existing CRT method, the shortened array code and the array code are usually used as the component codes to construct the SA code. The exponent matrices of FF code, FA code and SA code are given both for the overall graph and the lower graph. Bit error rate (BER) simulation results indicate that the proposed FF code and FA code are superior to the SA code both at the relay node and the destination node. In addition, the theoretical limit and the BER of the bilayer irregular LDPC code are also given to compare with the BER of the proposed QC-LDPC codes. Moreover, the proposed Biff-CRT method is flexible, easy to implement and effective for constructing the QC-LDPC codes for the relay channel, and it is attractive for being used in the future cooperative communication systems.

In this paper, we propose a new encoding method applicable to any linear codes over arbitrary finite field whose computational complexity is O(δ*n) where δ* and n denote the maximum column weight of a parity check matrix of a code and the code length, respectively. This means that if a code has a parity check matrix with the constant maximum column weight, such as LDPC codes, it can be encoded with O(n) computation. We also clarify the relation between the proposed method and conventional methods, and compare the computational complexity of those methods. Then we show that the proposed encoding method is much more efficient than the conventional ones.

Majority-logic algorithms are devised for decoding non-binary LDPC codes in order to reduce computational complexity. However, compared with conventional belief propagation algorithms, majority-logic algorithms suffer from severe bit error performance degradation. This paper presents a low-complexity reliability-based algorithm aiming at improving error correcting ability of majority-logic algorithms. Reliability measures for check nodes are novelly introduced to realize mutual update between variable message and check message, and hence more efficient reliability propagation can be achieved, similar to belief-propagation algorithm. Simulation results on NB-LDPC codes with different characteristics demonstrate that our algorithm can reduce the bit error ratio by more than one order of magnitude and the coding gain enhancement over ISRB-MLGD can reach 0.2-2.0dB, compared with both the ISRB-MLGD and IISRB-MLGD algorithms. Moreover, simulations on typical LDPC codes show that the computational complexity of the proposed algorithm is closely equivalent to ISRB-MLGD algorithm, and is less than 10% of Min-max algorithm. As a result, the proposed algorithm achieves a more efficient trade-off between decoding computational complexity and error performance.

In this letter, we present a new scheme to find small fundamental instantons (SFIs) of regular low-density parity-check (LDPC) codes for the linear programming (LP) decoding over the binary symmetric channel (BSC). Based on the fact that each instanton-induced graph (IIG) contains at least one short cycle, we determine potential instantons by constructing possible IIGs which contain short cycles and additional paths connected to the cycles. Then we identify actual instantons from potential ones under the LP decoding. Simulation results on some typical LDPC codes show that our scheme is effective, and more instantons can be obtained by the proposed scheme when compared with the existing instanton search method.

In this paper, we propose a message passing decoding algorithm which lowers decoding error rates in the error floor regions for non-binary low-density parity-check (LDPC) codes transmitted over the binary erasure channel (BEC) and the memoryless binary-input output-symmetric (MBIOS) channels. In the case for the BEC, this decoding algorithm is a combination with belief propagation (BP) decoding and maximum a posteriori (MAP) decoding on zigzag cycles, which cause decoding errors in the error floor region. We show that MAP decoding on the zigzag cycles is realized by means of a message passing algorithm. Moreover, we extend this decoding algorithm to the MBIOS channels. Simulation results demonstrate that the decoding error rates in the error floor regions by the proposed decoding algorithm are lower than those by the BP decoder.

This paper proposes an adaptive marker coding (AMC) for correction of insertion/deletion/substitution errors. Unlike the conventional marker codings which select marker-bit values deterministically, the AMC adaptively reverses the first and last bits of each marker as well as bits surrounding the marker. Decoding is based on a forward-backward algorithm which takes into account the dependency of bit-values around the marker. Evaluation shows that, for a channel with insertion/deletion error probability 1.8×10-2, the decoded BER of existing marker coding of rate 9/16 is 4.25×10-3, while that of the proposed coding with the same code rate is 1.73×10-3.

Given specified parameters, the number of check nodes, the expected girth and the variable node degrees, the Progressive Weight-Growth (PWG) algorithm is proposed to generate high rate low-density parity-check (LDPC) codes. Based on the theoretic foundation that is to investigate the girth impact by adding/removing variable nodes and edges of the Tanner graph, the PWG progressively increases column weights of the parity check matrix without violating the constraints defined by the given parameters. The analysis of the computational complexity and the simulation of code performance show that the LDPC codes by the PWG provide better or comparable performance in comparison with LDPC codes by some well-known methods (e.g., Mackay's random constructions, the PEG algorithm, and the bit-filling algorithm).

Single view distributed video coding (DVC) is a coding method that allows for the computational complexity of the system to be shifted from the encoder to the decoder. This property promotes the use of DVC in systems where processing power or energy use at the encoder is constrained. Examples include wireless devices and surveillance. This paper proposes a multi-hypothesis transform domain single-view DVC system that performs symbol level coding with a non-binary low-density parity-check code. The main contributions of the system relate to the methods used for combining multiple side information hypotheses at the decoder. The system also combines interpolation and extrapolation in the side information creation process to improve the performance of the system over larger group-of-picture sizes.

This paper derives the average symbol and bit weight distributions for the irregular non-binary cluster low-density parity-check (LDPC) code ensembles. Moreover, we give the exponential growth rates of the average weight distributions in the limit of large code length. We show the condition that the typical minimum distances linearly grow with the code length.

Spatially coupled (SC) low-density parity-check (LDPC) codes are defined by bipartite graphs that are obtained by assembling prototype graphs. The combination and connection of prototype graphs are designated by specifying some parameters, and Kudekar et al. showed that BP threshold of the ensemble of SC LDPC codes agrees with MAP threshold of the ensemble of regular LDPC codes when those parameters are grown up so that the code length tends to infinity. When we design SC LDPC codes with practical code length, however, it is not clear how to set those parameters to enhance the performance of SC LDPC codes. In this paper, we provide the result of numerical experiments that suggest the dependence of error performance of SC LDPC codes over BEC on their design parameters.

Bit-patterned medium (BPM) is one of the promising approaches for ultra-high density magnetic recording systems. However, BPM requires precise write synchronization, and exhibits write-errors due to insufficient write field gradient, medium switching field distribution (SFD), demagnetization field from adjacent islands, and island position variation. In this paper, an iterative decoding system using a non-binary low-density parity-check (LDPC) code is considered for a BPM R/W channel with write-errors at an areal recording density of 2Tbit/inch2 including the coding rate loss. The performance of the iterative decoding system using the non-binary LDPC code over the Galois field GF(28) is evaluated by computer simulation, and it is compared with the conventional iterative decoding system using a binary LDPC code. The results show that the non-binary LDPC system has a larger write margin than the binary LDPC system.

In this paper, we propose the construction of quasi-cyclic (QC) LDPC codes based on the modified progressive edge-growth (PEG) algorithm to achieve the maximum local girth. Although the previously designed QC-LDPC codes based on the PEG algorithm has more flexible code rates than the conventional QC-LDPC code, in the design process, multiple choices of the edges may be chosen. In the proposed algorithm, we aim to maximize the girth property by choosing the suitable edges and thus improve the error correcting performance. Simulation results show that the QC-LDPC codes constructed from the proposed method give higher proportion of high local girths than other methods, particularly, at high code rates. In addition, the proposed codes offer superior bit error rate and block error rate performances to the previous PEG-QC codes over the additive white Gaussian noise (AWGN) channel.

We propose an asynchronous datapath for the low-density parity-check decoder to decrease power consumption. Glitches and redundant computations are decreased by the asynchronous design. Taking advantage of the statistical characteristics of the input data, we develop novel key arithmetic elements in the datapath to reduce redundant computations. Two other types of datapaths, including normal synchronous design and clock-gating design, are implemented for comparisons with the proposed design. The three designs use similar architectures and realize the same function by using the 0.18µm process of the Semiconductor Manufacturing International Corporation. Post-layout result shows that the proposed asynchronous design exhibits the lowest power consumption. The proposed asynchronous design saves 48.7% and 21.9% more power than the normal synchronous and clock-gating designs, respectively. The performance of the proposed datapath is slightly worse than the clock-gating design but is better than the synchronous design. The proposed design is approximately 7% larger than the other two designs.

In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the IEEE 802.16e WiMAX standard. The decoder supports all the code rates and codeword lengths defined in the standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. In addition, the decoder adopts a novel scheduling scheme named stride scheduling, which stores the extrinsic messages in non-sequential order to replace the conventional complex flexible permutation network with simple small-sized cyclic shifters and also minimize the number of memory accesses. To further minimize the complexity, the number of extrinsic memory instances for 24 block columns is reduced to 5 banks by identifying independent sets. All the memory instances used in the decoder are single-port memories which cost less area and price compared to dual-port ones. Finally, the decoding function units have partially parallel structure to make the decoding throughput sufficiently over the requirement of the WiMAX standard. The proposed decoder is synthesized with 49 K equivalent gates and 54,144 bits of memory, and the implementation occupies 0.40 mm2 in a 65 nm CMOS technology.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

In this paper, through extrinsic information transfer (EXIT) band chart analysis, an adaptive iterative decoding approach (AIDA) is proposed to reduce the iterative decoding complexity and delay for finite-length differentially encoded Low-density parity-check (DE-LDPC) coded systems with multiple-symbol differential detection (MSDD). The proposed AIDA can adaptively adjust the observation window size (OWS) of the MSDD soft-input soft-output demodulator (SISOD) and the outer iteration number of the iterative decoder (consisting of the MSDD SISOD and the LDPC decoder) instead of setting fixed values for the two parameters of the considered systems. The performance of AIDA depends on its stopping criterion (SC) which is used to terminate the iterative decoding before reaching the maximum outer iteration number. Many SCs have been proposed; however, these approaches focus on turbo coded systems, and it has been proven that they do not well suit for LDPC coded systems. To solve this problem, a new SC called differential mutual information (DMI) criterion, which can track the convergence status of the iterative decoding, is proposed; it is based on tracking the difference of the output mutual information of the LDPC decoder between two consecutive outer iterations of the considered systems. AIDA using the DMI criterion can adaptively adjust the out iteration number and OWS according to the convergence situation of the iterative decoding. Simulation results show that compared with using the existing SCs, AIDA using the DMI criterion can further reduce the decoding complexity and delay, and its performance is not affected by a change in the LDPC code and transmission channel parameters.

In this letter, a low complexity decoder for non-binary low-density parity-check (LDPC) codes in a multiple-input and multiple-output (MIMO) channel is proposed employing Quasi-orthogonal space-time block code (QOSTBC). The complexity of the proposed decoding algorithm involved grows linearly with the number of transmit antennas and order of Galois Field.

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 2448 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36 mm2 in SMIC 65 nm CMOS process, and realizes 1056 Mbps throughput at 1.2 V, 110 MHz and 10 iterations with 115 mW power occupation, which infers a power efficiency of 10.9 pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.

In this paper, we compare the decoding error rates in the error floors for non-binary low-density parity-check (LDPC) codes over general linear groups with those for non-binary LDPC codes over finite fields transmitted through the q-ary memoryless symmetric channels under belief propagation decoding. To analyze non-binary LDPC codes defined over both the general linear group GL(m, F2) and the finite field F2m, we investigate non-binary LDPC codes defined over GL(m3, F2m4). We propose a method to lower the error floors for non-binary LDPC codes. In this analysis, we see that the non-binary LDPC codes constructed by our proposed method defined over general linear group have the same decoding performance in the error floors as those defined over finite field. The non-binary LDPC codes defined over general linear group have more choices of the labels on the edges which satisfy the condition for the optimization.

From an information-theoretic point of view, it is well known that the capacity of relay channels comprising of three terminals is much greater than that of two terminal direct channels especially for low SNR region. Previously invented relay coding strategies have not been designed to achieve this relaying gain occurring in the low SNR region. In this paper, we propose a new simple coding strategy for a relay channel with low SNR or, equivalently, for a very noisy relay channel. The multiplicative repetition is utilized to design this simple coding strategy. We claim that the proposed strategy is simple since the destination and the relay can decode with almost the same computational complexity by sharing the same structure of decoder. An appropriate static power allocation which yields the maximum throughput close to the optimal one in low SNRs is also suggested. Under practical constraints such as equal time-sharing etc., the asymptotic performance of this simple strategy is within 0.5 dB from the achievable rate of a relay channel. Furthermore, the performance at few thousand bits enjoys a relaying gain by approximately 1 dB.