Kudekar et al. recently proved that for transmission over the binary erasure channel (BEC), spatial coupling of LDPC codes increases the BP threshold of the coupled ensemble to the MAP threshold of the underlying LDPC codes. One major drawback of the capacity-achieving spatially-coupled LDPC codes is that one needs to increase the column and row weight of parity-check matrices of the underlying LDPC codes. It is proved, that Hsu-Anastasopoulos (HA) codes and MacKay-Neal (MN) codes achieve the capacity of memoryless binary-input symmetric-output channels under MAP decoding with bounded column and row weight of the parity-check matrices. The HA codes and the MN codes are dual codes each other. The aim of this paper is to present an empirical evidence that spatially-coupled MN (resp. HA) codes with bounded column and row weight achieve the capacity of the BEC. To this end, we introduce a spatial coupling scheme of MN (resp. HA) codes. By density evolution analysis, we will show that the resulting spatially-coupled MN (resp. HA) codes have the BP threshold close to the Shannon limit.

In this paper, we investigate the error floors of non-binary low-density parity-check (LDPC) codes transmitted over the memoryless binary-input output-symmetric (MBIOS) channels. We provide a necessary and sufficient condition for successful decoding of zigzag cycle codes over the MBIOS channel by the belief propagation decoder. We consider an expurgated ensemble of non-binary LDPC codes by using the above necessary and sufficient condition, and hence exhibit lower error floors. Finally, we show lower bounds of the error floors for the expurgated LDPC code ensembles over the MBIOS channels.

This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.

The fixed points of the belief propagation decoder for non-binary low-density parity-check (LDPC) codes are referred to as stopping constellations. In this paper, we give the stopping constellation distributions for the irregular non-binary LDPC code ensembles defined over the general linear group. Moreover, we derive the exponential growth rate of the average stopping constellation distributions in the limit of large codelength.

Adaptive network coded cooperation (ANCC) scheme may have excellent performance for data transmission from a large collection of terminals to a common destination in wireless networks. However, the random relay selection strategy for ANCC protocol may generate the distributed low-density parity-check (LDPC) codes with many short cycles which may cause error floor and performance degradation. In this paper, an optimized relay selection strategy for ANCC is proposed. Before data communication, by exploiting low-cost information interaction between the destination and terminals, the proposed method generates good assembles of distributed LDPC codes and its storage requirement reduces dramatically. Simulation results demonstrate that the proposed relay selection protocol significantly outperforms the random relay selection strategy.

In this letter, we propose an appealing class of nonbinary quasi-cyclic low-density parity-check (QC-LDPC) cycle codes. The parity-check matrix is carefully designed such that the corresponding generator matrix has some nice properties: 1) systematic, 2) quasi-cyclic, and 3) sparse, which allows a parallel encoding with low complexity. Simulation results show that the performance of the proposed encoding-aware LDPC codes is comparable to that of the progressive-edge-growth (PEG) constructed nonbinary LDPC cycle codes.

In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

Low-density parity-check (LDPC) codes are typically designed to avoid the length-4 cycles to ensure acceptable levels of performance. However, the turbo equalization, which relies on an interaction between an inner code such as an LDPC code and a soft-output Viterbi algorithm (SOVA) detector, exhibits a performance degradation due to the pseudo cycles. In this paper, we propose an interleaved modified array code (IMAC) that can reduce the number of pseudo cycles, hence, improving the gains from the iterative processing technique. The modification is made on the existing array-based LDPC codes named modified array codes (MAC) by introducing an additional interleaving matrix to the parity-check matrix. Simulation results on the perpendicular magnetic recording channels (PMRC) demonstrate that the IMAC outperforms both the MAC and the previously proposed random interleave array (RIA) codes for the partial-response targets under consideration. In addition, a subblock-based encoder design is proposed to reduce the encoding complexity of the IMAC and when compared with the RIA code, the IMAC exhibits a lower encoding complexity, and still maintains a comparable level of the decoding complexity.

In this paper, we propose a reduced complexity algorithm for blind frame synchronization based on code-constraints in a quasi-cyclic low density parity check (QC-LDPC) coded system. It can be used for both hard and soft synchronizers. For soft synchronizers, we present a modified algorithm that achieves better performance at high signal to noise ratio (SNR). Analysis indicates that the proposed algorithm has low complexity for hardware implementation.

This paper shows a fast estimation method of very low error rate of low-density parity-check (LDPC) codes. No analytical tool is available to evaluate performance of LDPC codes, and the traditional Monte Carlo simulation methods can not estimate the low error rate of LDPC codes due to the limitation of time. To conquer this problem, we propose another simulation method which is based on the optimal simulation probability density function (PDF). The proposed simulation PDF can also avoid the dependency between the simulation time and the number of dominant trapping sets, which is the problem of some fast simulation methods based on the error event simulation method. Additionally, we show some numerical examples to demonstrate the effectiveness of the proposed method. The simulation time of the proposed method is reduced to almost less than 1/10 of that of Cole et al.'s method under the condition of the same accuracy of the estimator.

In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.

Multiple-input multiple-output (MIMO) OFDM technique is an attractive solution to increase the spectrum efficiency for mobile transmission applications. However, high spatial correlation makes signal detection difficult in real outdoor environments, and thus various methods have been developed to improve the detection performance. An iterative low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) system is a promising method for solving this problem, and its performance has been analyzed theoretically. This paper proposes an iterative LDPC minimum mean square error with soft interference cancellation (LDPC-MMSE-SIC) receiver with a time de-interleaver in front of the MMSE detector and evaluates its performance by computer simulation using channel state information (CSI) acquired in real outdoor measurements. We show that the iterative detection and decoding system with time interleaving, which is long enough to cover a fading cycle, achieves excellent error rate performance in mobile LOS environments and outperforms an LDPC maximum likelihood detection (LDPC-MLD) receiver with the same error correction and interleaving.

For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

In this paper, we consider the behavior of an autoregressive (AR) detector for partial-response (PR) signaling against offtrack interference (OTI) environment in perpendicular magnetic recording. Based on the behavior, we derive the optimum branch metric to construct the detector by the Viterbi algorithm. We propose an optimum AR detector for OTI that considers an optimum branch metric calculation and an estimation of noise power due to OTI in order to calculate an accurate branch metric. To evaluate the reliability of soft-output likelihood values calculated by our proposed AR detector, we demonstrate a bit error rate performance (BER) of low-density parity-check (LDPC) codes under OTI existing channel by computer simulation. Our simulation results show the proposed AR detector can achieve a better LDPC-coded BER performance than the conventional AR detector. We also show the BER performance of our proposal can keep within 0.5 dB of the case that perfect channel state information regarding OTI is used in the detector. In addition, we show that the partial-response maximum-likelihood (PRML) detector is robust against OTI even if OTI is not handled by the detector.

Recently, Mooij et al. proposed new sufficient conditions for convergence of the sum-product algorithm, and it was also shown that if the factor graph is a tree, Mooij's sufficient condition for convergence is always activated. In this letter, we show that the converse of the above statement is also true under some assumption, and that the assumption holds for the sum-product decoding. These newly obtained fact implies that Mooij's sufficient condition for convergence of the sum-product decoding is activated if and only if the factor graph of the a posteriori probability of the transmitted codeword is a tree.

In this letter, an NB RCP LDPC (Non-Binary Rate-Compatible-Punctured Low Density Parity Check) code has been designed over the extended Galois Field. The designed code enables us to change the code rate easily by properly puncturing the appropriate symbols from the LDPC mother code. The designed NB RCP LDPC code has been applied to the Type II HARQ (Hybrid Automatic Repeat reQuest) scheme using OFDM (Orthogonal Frequency Division Multiplexing) modulation. The throughput characteristics of the proposed HARQ scheme are evaluated through computation simulation.

In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned into four unequal sub-matrices that lead to high efficiency in hardware sharing. As a result, it can handle two different codewords simultaneously with 100% hardware utilization. Furthermore, for minimizing the performance loss due to round-off errors in fixed-point implementations, the well-known modified min-sum decoding algorithm is enhanced by our recently proposed high-performance CMVP decoding algorithm. Overall, the proposed decoder has high throughput, low complexity, and good BER performances. In the circuit implementation example of the (576,288) parity check matrix for IEEE 802.16e standard, the decoder achieves a data rate of 5.5 Gbps assuming 10 decoding iterations and 7 quantization bits, with a small area of 653 K gates, based on UMC 90 nm process technology.

As described in this paper, construction and blind estimation methods of phase sequences are proposed for subcarrier-phase control based peak-to-average power ratio (PAPR) reduction in low-density parity-check (LDPC)-coded orthogonal frequency division multiplexing (OFDM) systems. On the transmitter side, phase sequence patterns are constructed based on a given parity-check matrix. The PAPR of the OFDM signal is reduced by multiplying the constructed phase sequence selected from the same number of candidates as the number of weighting factor (WF) combinations in a partial transmit sequence (PTS) method. On the receiver side, the phase sequence is estimated blindly using the decoding function, i.e., the most likely phase sequence among a limited number of possible phase sequence candidates is inferred by comparing the sum-product calculation results of each candidate. Computer simulation results show that PAPR of QPSK-OFDM and 16QAM-OFDM signals can be reduced respectively by about 3.7 dB and 4.0 dB without marked degradation of the block error rate (BLER) performance as compared to perfect estimation in an attenuated 12-path Rayleigh fading condition.