The increasing demand for millimeter-wave (mmWave) frequencies with wider signal bandwidths, such as 5G NR, requires large investments on test equipment. This work presents a 5G mmWave up/down-converter with a 40 GHz LO, fabricated in custom PCBs with off-the-shelf components. The mmWave converter has broad IF and RF bandwidths of 1∼5 GHz and 21∼45 GHz, and the built-in LO generates 20∼29.5 GHz and 33.5∼40 GHz of output. To achieve high linearity of the converter simultaneously, the LO must produce low-phase-noise and be capable of high harmonics/spur rejection, and design techniques related to these features are demonstrated. Additionally, a reconfigurable IF amplifier for bi-directional conversion is included and demonstrates low gain variation to maintain the linearity of the wideband modulation signals. The final designed converter is tested with 5G OFDM 64-QAM 100 MHz 1-CC (4-CC) signals and shows RF/IF output power of -3/8 dBm with a linear range of 35 (30)/38 (33) dB at an EVM of 25 dB.

This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.

A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.

This paper proposes two linearity enhancement techniques for open-loop amplifiers. One technique is nonlinearity cancellation. An amplifier with reversed nonlinearity is proposed to cascade with a conventional common source amplifier. The product of these two nonlinear gains demonstrates much higher linearity. It achieves a SFDR of 71 dB when differential output range is 600 mV. Compared with the conventional common source amplifier, about 24 dB improvement is achieved. Another proposed technique is gain adapting. An input amplitude detector utilizing second order nonlinearity is combined with a source-degenerated amplifier. It can adjust the gain automatically according to the input amplitude, and compensate the gain compression when the input amplitude becomes larger. A SFDR of 69 dB is realized when the differential output range is 600 mV. An improvement of 23 dB is achieved after gain is adapted. Furthermore, mismatch calibration for the two proposed linearity enhancement techniques is investigated. Finally, comparison between two proposed amplifiers is introduced. The amplifier with nonlinearity cancellation has advantage in large signal range while the amplifier utilizing gain adapting is more competitive on accurate calibration, fast response and low noise.

A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.