This work shows a broadband, high-efficiency power amplifier (PA) monolithic microwave integrated circuit (MMIC) that uses InP-based metal-oxide-semiconductor (MOS) high-electron-mobility transistors (HEMTs) with an extended drain-side access region and broadband conjugate matching topology. Advanced device technologies, namely, double-side-doped structures, MOS gate structures, and asymmetric gate recess, were adopted, and the length of the drain-side access region was optimized to simultaneously obtain high power and efficiency. A common-source PA MMIC based on InP-based MOS-HEMTs was fabricated, and an interstage circuit was designed to maximize the S21 per unit stage in the broadband, resulting in a record-high power-added efficiency and wide bandwidth.

In this study, AM-PM compensation of the cross-coupled capacitance neutralization technique is discussed. Cgd neutralization leads to AM-PM compensation of a power amplifier with negligible change of AM-AM characteristics. AM-PM compensation was confirmed via circuit analysis and measurements. The formulation analysis showed that AM-PM compensation can be derived via gm variation against input power with capacitance neutralization. A differential power amplifier with capacitance neutralization was fabricated with GaN high-electron-mobility transistors. The AM-PM characteristic of the fabricated differential power amplifier was measured at 17.7 GHz. It showed AM-PM reduction of 22° at compared to a single-phase power amplifier without capacitance neutralization at output power of 35 dBm.

This paper reports on X-band Gallium Nitride (GaN) chipsets for cost-effective 20W transmit-receive (T/R) modules. The chipset components include a GaN-on-Si monolithic microwave integrated circuit (MMIC) driver amplifier (DA), a GaN-on-SiC high power amplifier (HPA) with GaAs matching circuits, a high-gain GaN-on-Si HPA with a GaAs output matching circuit, and a GaN-on-Si MMIC switch (SW). By utilizing either combination of the DA or single high-gain HPA, the configurations of two T/R module types can be realized. The GaN-on-Si MMIC DA demonstrates an output power of 6.4-7.4W, an associate gain of 22.3-24.6dB and a power added efficiency (PAE) of 32-36% over 9.0-11.0GHz. A GaN-on-SiC HPA with GaAs matching circuits exhibited an output power of 20-28W, associate gain of 7.8-10.7dB, and a PAE of 40-56% over 9.0-11.0GHz. The high-gain GaN-on-Si HPA with a GaAs output matching circuit exhibits an output power of 15-30W, associate gain of 27-30dB, and PAE of 26-33% over 9.0-11.0GHz. The GaN-on-Si MMIC switch demonstrates insertion losses of 1.1-1.3dB and isolation of 10.1-14.7dB over 8.0-11.5GHz. By employing cost-effective circuit configurations, the costs of these chipsets are estimated to be about half that of conventional chipsets.

A methodology for obtaining semi-custom high-power amplifiers (HPAs) is described. The semi-custom concept pertains to the notion that a selectable output power is attainable by replacing only transistors. To compensate for the mismatch loss, a new output matching network that can be easily tuned by wiring is proposed. Design equations were derived to determine the circuit parameters and specify the bandwidth limitations. To verify this methodology, a semi-custom HPA with GaN HEMTs was fabricated in the S-band. A selectable output power from 240 to 150 W was successfully achieved while maintaining a PAE of over 50% in a 19% relative bandwidth.

A TM010 cavity power combiner is presented, which achieves direct interface to microstrip lines via magnetic field coupling. A prototype is fabricated and its S-matrix measured. From the S-parameters we calculate that it shows less than 0.85 dB insertion loss over 250 MHz bandwidth at X-band. The return power to the input ports is less than -15 dB over this bandwidth. We verify the insertion loss estimation using S-matrix, by measuring transmission S-parameter of a concatenated 2-port divider-combiner network. Similarly analyzed is the case of performance of power combiner when one of the input fails. We find that we can achieve graceful degradation provided we ensure some particular reflection phase at the degraded port.

In this paper we describe and experimentally validate a dual-band digital predistortion (DPD) model we propose that takes account of the intermodulation and harmonic distortion produced when the center frequencies of input bands have a harmonic relationship. We also describe and experimentally validate our proposed novel dual-band power amplifier (PA) linearization architecture consisting of a single feedback loop employing a dual-band mixer. Experiment results show that the DPD linearization the proposed model provides can compensate for intermodulation and harmonic distortion in a way that the conventional two-dimensional (2-D) DPD approach cannot. The proposed feedback architecture should make it possible to simplify analog-to-digital converter (ADC) design and eliminate the time lag between different feedback paths.

Design equations for satisfying off-nominal operating conditions of the class E amplifier with a nonlinear shunt capacitance for a grading coefficient of 0.5 and the duty cycle D=0.5 are derived. By exploiting the off-nominal class E operation, various amplifier parameters such as input voltage, operating frequency, output power, and load resistance can be set as design specifications. As a result of the analysis in this paper, the following extension of the usability of the class E amplifier was achieved. With rising up the dc supply voltage, the shunt capacitance which achieves the off-nominal operation can be increased. This means that a transistor with higher output capacitance can be used for ZVS operation. This also means that maximum operating frequency which achieves ZVS can be increased. An example of a design procedure of the class E amplifier is given. The theoretical results were verified with an experiment.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LC-tank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are moved to the left half plane, improving the common-mode stability. The simulation results show that the new method is an effective way to stabilize the PA.

We present an analytical nonlinear adiabatic theory of the microwave electron device that we call the Autophase Microwave Tube (AMT). In contrast to the well-known Traveling Wave Tube (TWT), the AMT exploits a highly efficient non-synchronous beam-wave interaction for the amplification (or generation) of the HF electromagnetic waves, and, differently from klystron and such hybrid devices as twystron, it employs a continuous beam-wave interaction. Because of these distinctive features, the AMT presents a special class of microwave electron devices, which feature very high electronic efficiency (which tends to 100%) and large bandwidth. Here, we develop the theory that allows one to find the profiles of static longitudinal electric or magnetic field (or both) over the device length, which yield negligible de-bunching together with highly efficient amplification (generation) of the HF electromagnetic wave. The analysis of electron motion in the bunch is performed by means of Lyapunov stability theory. The numerical example illustrates the possibility of achieving the electronic efficiency of AMT as high as 92%. We compare different autophase regimes in the AMT and show that the profiling of the longitudinal static magnetic focusing field in the helix AMT with the non-azimuthally symmetric wave has many advantages with respect to other regimes.

An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

An inter-modulation distortion (IMD) compensation method for thermal memory effect using a multistage RC-ladder circuit has been proposed. The IMD caused by the thermal memory effect on an InGaP/GaAs HBT amplifier was compensated for by inserting a multistage RC-ladder circuit in the base bias circuit of the amplifier. Since heat flux owing to self-heating in the transistor can be approximated with a multistage thermal RC-ladder circuit, the canceling of IMD by an additional electrical memory effect generated from the RC-ladder circuit is predicted. The memory effects cause asymmetrical characteristics between upper and lower IMD. The IMD caused by the memory effects is expressed as a vector sum of each origin. By adjusting an electrical reactance characteristic for sub-harmonics affected by the thermal memory effect in the amplifier circuit, the asymmetric characteristic is symmetrized. The parameters of the RC-ladder circuit were estimated so that the adjusted electrical reactance characteristic is reproduced in simulation. A fabricated InGaP/GaAs HBT amplifier with the thermal memory effect compensation circuit exhibited a symmetrized and suppressed IMD characteristics.

Nonlinear distortions in power amplifiers (PAs) generate spectral regrowth at the output, which causes interference to adjacent channels and errors in digitally modulated signals. This paper presents a novel method to evaluate adjacent channel leakage power ratio (ACPR) and error vector magnitude (EVM) from the amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) characteristics. The transmitted signal is considered to be complex Gaussian distributed in orthogonal frequency-division multiplexing (OFDM) systems. We use the Mehler formula to derive closed-form expressions of the PAs output power spectral density (PSD), ACPR and EVM for memoryless PA and memory PA respectively. We inspect the derived relationships using an OFDM signal in the IEEE 802.11a WLAN standard. Simulation results show that the proposed method is appropriate to predict the ACPR and EVM values of the nonlinear PA output in OFDM systems, when the AM/AM and AM/PM characteristics are known.

We have developed a power amplifier IC for Bluetooth Class 1 operating at single low voltage of 1.8 V for both control and drain voltages. We can realize it due to fully enhancement-mode hetero-junction FETs utilizing a re-grown p +-GaAs gate technology. The power amplifier is a highly compact design as a small package of 1.5 mm1.5 mm0.4 mm with fully integrated gain control and shutdown functions. An impressive power added efficiency of 52% at an output power of 20 dBm is achieved with an associated gain of 22 dB. Also, sufficiently low leakage current of 0.25 µA at 27 is exhibited, which is comparable to conventional HBT power amplifiers.

Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.

This report presents Dual Field-modulating-Plates (Dual-FP) technology for a 28 V operated high power GaAs heterojunction FET (HJFET) amplifier. A developed HJFET has two FP electrodes; the 1st-FP is connected to the gate and the 2nd-FP to the ground. The 2nd-FP suppresses the drain current dispersion effectively cooperating with the 1st-FP, and it can also reduce the gate-drain parasitic capacitance. The developed push-pull amplifier, with four Dual-FPFET chips, demonstrated 55.1 dBm (320 W) output power with a 14.0 dB linear gain and a drain efficiency of 62% at 2.14 GHz. Under two-carrier W-CDMA signals, it showed a high drain efficiency of 30% and low third-order Inter-modulation distortion of -37 dBc at output power of 47.5 dBm.

An improved methodology, based on the genetic algorithm, is developed to design thermal-via structures and circuit parameters of advanced InGaP and InGaAs collector-up heterojunction bipolar transistors (C-up HBTs), which are promising miniature high-power amplifiers (HPAs) in cellular communication systems. Excellent simulated and measured results demonstrate the usefulness of this technique.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

We propose a novel adaptive linearization technique for a balanced-amplifier array. The technique uses the specific intermodulation distortions (IMDs) at the output ports in the array. The detected IMD power level can be used to optimize the linearizer's characteristics. Because the design does not need as many power detectors and carrier cancel loops as it does amplifiers, we were able to successfully miniaturize the array-antenna system. This paper describes the principles, verified both experimentally and mathematically for a 4-port amplifier array.

A novel scheme for a multi-band power amplifier (PA) that employs a low-loss reconfigurable matching network is presented and discussed. The matching network basically consists of a cascade of single-stub tuning circuits, in which each stub is connected to a transmission line via a Single-Pole-Single-Throw (SPST) switch. By controlling the on/off status of each switch, the matching network works as a band-switchable matching network. Based on a detailed analysis of the influence of non-ideal switches in the matching network, we conceived a new design perspective for the reconfigurable matching network that achieves low loss. A 900/1900-MHz dual-band, 1 W class PA is newly designed following the new design perspective, and fabricated with microelectro mechanical system (MEMS) SPST switches. Owing to the new design and sufficient characteristics of the MEMS switches, the dual-band PA achieves over 60% of the maximum power-added efficiency with an output power for each band exceeding 30 dBm. These results are comparable to the estimated results for a single-band PA. This shows that the proposed scheme provides a band-switchable highly efficient PA that has superior performance compared to the conventional multi-band PA that has a complex structure.