Author Search Result

[Author] Yoshihiro TSUKAHARA(4hit)

1-4hit
  • A Compact Wideband T/R Switching Circuit Utilizing Quadrature Couplers and Gate-and-Drain-Driven HPAs

    Hiromitsu UCHIDA  Masatoshi NII  Norio TAKEUCHI  Yoshihiro TSUKAHARA  Moriyasu MIYAZAKI  Yasushi ITOH  

     
    PAPER

      Vol:
    E85-C No:12
      Page(s):
    2022-2028

    A novel compact T/R (Transmit/Receive) switching circuit for wideband T/R modules has been proposed. It employs quadrature couplers and gate-and-drain-driven HPAs to remove circulators or T/R switches from a conventional T/R module, and T/R switching is made with controlling biasing conditions of the FETs in HPAs. Furthermore, an optimum biasing condition and design of output matching circuit of the HPA have been studied to reduce loss in RX-mode, and the validity of the method has been confirmed by measurements.

  • A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs

    Hidenori YUKAWA  Masatoshi NII  Yoshihiro TSUKAHARA  Yukio IKEDA  Yasushi ITOH  

     
    PAPER

      Vol:
    E85-C No:12
      Page(s):
    2029-2035

    A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.

  • MMIC/Super-MIC/MIC-Combined C- to Ku-Band 2 W Balanced Amplifier Multi-Chip Module

    Yasushi ITOH  Masatoshi NII  Norio TAKEUCHI  Yoshihiro TSUKAHARA  Hidetoshi KUREBAYASHI  

     
    PAPER

      Vol:
    E80-C No:6
      Page(s):
    757-762

    This paper describes the design, fabrication, and performance of a C- to Ku-band 2 W balanced amplifier multi-chip module employing an MMIC/Super-MIC/MIC configuration. In this module, single-ended amplifiers, quadrature couplers, and pulsed-drive circuits are fabricated on MMICs, Super-MICs, and MICs, respectively, which show different features in fabrication, performance, size, and cost. With the use of the distinguished features of MMICs, Super-MICs, and MICs, the multi-chip module with high performance, small size, and low cost has been achieved. The MMIC/Super-MIC/MIC-combined module would be a candidate for a variety of multi-chip modules with stringent requirements for performance, size, and cost.

  • On-Chip Temperature Compensation Active Bias Circuit Having Tunable Temperature Slope for GaAs FET MMIC PA

    Shintaro SHINJO  Kazutomi MORI  Tomokazu OGOMI  Yoshihiro TSUKAHARA  Mitsuhiro SHIMOZAWA  

     
    PAPER-Active Devices and Circuits

      Vol:
    E94-C No:10
      Page(s):
    1498-1507

    An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

FlyerIEICE has prepared a flyer regarding multilingual services. Please use the one in your native language.