High availability is crucial for industrial Ethernet networks and Ethernet-based control systems, such as automation networks and substation automation systems. Because the standard Ethernet does not support fault tolerance capability, the high availability of Ethernet networks can be increased by using redundancy protocols. Various redundancy protocols for Ethernet networks have been developed and standardized, such as rapid spanning tree protocol (RSTP), media redundancy protocol (MRP), parallel redundancy protocol (PRP), high-availability seamless redundancy (HSR), and others. RSTP and MRP provide redundancy in the network, whereas PRP and HSR provide redundancy in the end nodes. RSTP and MRP have a disadvantage in switchover delay. PRP and HSR provide zero recovery time, but PRP requires a duplicate network infrastructure, and HSR is mainly used in ring-based topologies. Additionally, PRP and HSR provide seamless redundancy in the end nodes and are applied in dedicated HSR networks with dedicated HSR nodes. In this paper, we present a novel seamless redundancy protocol for Ethernet networks, which is called the Redundancy Protocol for Ethernet (RPE). The RPE provides seamless redundancy in the network. This protocol not only provides seamless communications with zero switchover time in case of failure but also supports all topologies. The RPE is transparent and compatible with standard Ethernet nodes. These features make the RPE very useful in time-critical and mission-critical systems, such as substation automation systems, automation networks, and other industrial Ethernet networks.

A generalization of compression via substring enumeration (CSE) for k-th order Markov sources with a finite alphabet is proposed, and an upper bound of the codeword length of the proposed method is presented. We analyze the worst case maximum redundancy of CSE for k-th order Markov sources with a finite alphabet. The compression ratio of the proposed method asymptotically converges to the optimal one for k-th order Markov sources with a finite alphabet if the length n of a source string tends to infinity.

In 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) systems, when HARQ (Hybrid Automatic Repeat request) retransmission is invoked, the data at the transmitter are retransmitted randomly or sequentially regardless of their relationship to the wrongly decoded data. Such practice is inefficient since precious transmission resources will be spent to retransmit data that may be of no use in error correction at the receiver. This paper proposes an incremental redundancy HARQ scheme based on Error Position Estimating Coding (ePec) and LDPC (Low Density Parity Check Code) channel coding, which is called ePec-LDPC HARQ. The proposal is able to feedback the wrongly decoded code blocks within a specific MAC (Media Access Control) PDU (Protocol Data Unit) from the receiver. The transmitter gets the feedback information and then performs targeted retransmission. That is, only the data related to the wrongly decoded code blocks are retransmitted, which can improve the retransmission efficiency and thus reduce the retransmission overload. An enhanced incremental redundancy LDPC coding approach, called EIR-LDPC, together with a physical layer framing method, is developed to implement ePec-LDPC HARQ. Performance evaluations show that ePec-LDPC HARQ reduces the overall transmission resources by 15% compared to a conventional LDPC HARQ scheme. Moreover, the average retransmission times of each MAC PDU and the transmission delay are also reduced considerably.

As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in LSIs. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this paper, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources is available.

The high-availability seamless redundancy (HSR) protocol is a representative protocol that fulfills the reliability requirements of the IEC61850-based substation automation system (SAS). However, it has the drawback of creating unnecessary traffic in a network. To solve this problem, a dual virtual path (DVP) algorithm based on HSR was recently presented. Although this algorithm dramatically reduces network traffic, it does not consider the substation timing requirements of messages in an SAS. To reduce unnecessary network traffic in an HSR ring network, we introduced a novel packet transmission (NPT) algorithm in a previous work that considers IEC61850 message types. To further reduce unnecessary network traffic, we propose an extended dual virtual paths (EDVP) algorithm in this paper that considers the timing requirements of IEC61850 message types. We also include sending delay (SD), delay queue (DQ), and traffic flow latency (TFL) features in our proposal. The source node sends data frames without SDs on the primary paths, and it transmits the duplicate data frames with SDs on the secondary paths. Since the EDVP algorithm discards all of the delayed data frames in DQs when there is no link or node failure, unnecessary network traffic can be reduced. We demonstrate the principle of the EDVP algorithm and its performance in terms of network traffic compared to the standard HSR, NPT, and DVP algorithm using the OPNET network simulator. Throughout the simulation results, the EDVP algorithm shows better traffic performance than the other algorithms, while guaranteeing the timing requirements of IEC61850 message types. Most importantly, when the source node transmits heavy data traffic, the EDVP algorithm shows greater than 80% and 40% network traffic reduction compared to the HSR and DVP approaches, respectively.

Cloud storage has become popular and is being used to hold important data. As a result, availability to become important; cloud storage providers should allow users to upload or download data even if some part of the system has failed. In this paper, we discuss distributed cloud storage that is robust against failures. In distributed cloud storage, multiple replicas of each data chunk are stored in the virtual storage at geographically different locations. Thus, even if one of the virtual storage systems becomes unavailable, users can access the data chunk from another virtual storage system. In distributed cloud storage, the placement of the virtual storage system is important; if the placement of the virtual cloud storage system means that a large number of virtual storages are possible could become unavailable from a failure, a large number of replicas of each data chunk should be prepared to maintain availability. In this paper, we propose a virtual storage placement method that assures availability with a small number of replicas. We evaluated our method by comparing it with three other methods. The evaluation shows that our method can maintain availability while requiring only with 60% of the network costs required by the compared methods.

Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.

This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.

Lossy communication networks may be one of the most challenging issues for Transmission Control Protocol (TCP), as random loss could be erroneously interpreted into congestion due to the original mechanism of TCP. Network coding (NC) promises significant improvement in such environment thanks to its ability to mix data across time and flows. Therefore, it has been proposed to combine with TCP called TCP-NC by MIT. In this paper, we dedicated to quantifying the R, a key parameter for redundant packets, and make it close to the loss rate as much as possible, which has not been considered in the previous research. All of these are done by the sender who is completely unconscious of the network situation. Simulation results by NS2 under both wired and wireless networks showed that our method retains all the advantages of TCP-NC, and meanwhile outperforms TCP-NC and the other TCP variants in time-varying lossy networks.

While Triple modular Redundancy (TMR) is effective in eliminating soft errors in LSIs, the overhead of the triplicated area as well as the triplicated energy consumption is the problem. In addition to the spatial TMR mode where executions are simply tripricated and the majority is taken, the temporal TMR mode is available where only two copies of an operation are executed and the results are compared, then if the results differ, the third copy is executed to get the correct result. Appropriately selecting the power supply voltage is also an effective technique to reduce the energy consumption. In this paper, a method to derive a TMR design is proposed which selects the TMR mode and supply voltage for each operation to minimize the energy consumption within the time and area constraints.

Razor Flip-Flop (FF) is a good combination for the dynamic voltage scaling (DVS) technique to achieve high energy efficiency. We previously proposed a RazorProtector scheme, which uses, under a very high IR-drop zone, a redundant data-path to provide a very fast recovery for a Razor-FF based processor. In this paper, we propose a dynamic method to adjust the redundancy level to fine-grained fit both the program behaviors and processor manufacturing variations so as to achieve an optimal power saving. We design an online turning method to adjust the redundancy level according to the most related parameters, ILP (Instruction Level Parallelism) and DCF (Delay Criticality Factor). Our simulation results show that under a workload suite with different behaviors, the adaptive redundancy can achieve better Energy Delay Product (EDP) reduction than any static controls. Compared to the traditional application of Razor-FF and DVS, our proposed dynamic control achieves an EDP reduction of 56% in average for the workloads we studied.

Dubé and Beaudoin proposed a lossless data compression called compression via substring enumeration (CSE) in 2010. We evaluate an upper bound of the number of bits used by the CSE technique to encode any binary string from an unknown member of a known class of k-th order Markov processes. We compare the worst case maximum redundancy obtained by the CSE technique for any binary string with the least possible value of the worst case maximum redundancy obtained by the best fixed-to-variable length code that satisfies the Kraft inequality.

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves ‘detecting’ and ‘switching’, rather than ‘recovering’ from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

In this paper we consider fixed-to-fixed length (FF) coding of a general source X with vanishing error probability and define two kinds of optimalities with respect to the coding rate and the redundancy, where the redundancy is defined as the difference between the coding rate and the symbolwise ideal codeword length. We first show that the infimum achievable redundancy coincides with the asymptotic width W(X) of the entropy spectrum. Next, we consider the two sets $mCH(X)$ and $mCW(X)$ and investigate relationships between them, where $mCH(X)$ and $mCW(X)$ denote the sets of all the optimal FF codes with respect to the coding rate and the redundancy, respectively. We give two necessary and sufficient conditions corresponding to $mCH(X) subseteq mCW(X)$ and $mCW(X) subseteq mCH(X)$, respectively. We can also show the existence of an FF code that is optimal with respect to both the redundancy and the coding rate.

Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.

This paper investigates potential to improve fault-detection coverage by means of on-chip redundancy. The international standard on functional safety, namely, IEC61508 Ed. 2.0 Part 2 Annex E.3 prescribes the upper bound of βIC (common cause failure (CCF) ratio to all failures) is 0.25 to satisfy frequency upper bound of dangerous failure in the safety function for SIL (Safety Integrated Level) 3. On the other hand, this paper argues that the βIC does not necessarily have to be less than 0.25 for SIL 3, and that the upper bound of βIC can be determined depending on failure rate λ and CCF detection coverage. In other words, the frequency upper bound of dangerous failure for SIL3 can also be satisfied with βIC higher than 0.25 if the failure rate λ is lower than 400[fit]. Moreover, the paper shows that on-chip redundancy has potential to satisfy SIL 4 requirement; the frequency upper bound of dangerous failure for SIL4 can be satisfied with feasible ranges of βIC, λ and CCF coverage which can be realized by redundant code.

Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. Since it is a compute-intensive process which adversely affects performance, hardware acceleration using FPGAs has been tried and satisfactory performance has been achieved. However, recent extended usage of networks and storage systems require various correction capabilities for various CRC standards. Traditional hardware designs based on the LFSR (Linear Feedback Shift Register) tend to have fixed structure without such flexibility. Here, fully-adaptable CRC accelerator based on a table-based algorithm is proposed. The table-based algorithm is a flexible method commonly used in software implementations. It has been rarely implemented with the hardware, since it is believed that the operational speed is not enough. However, by using pipelined structure and efficient use of memory modules in FPGAs, it appeared that the table-based fixed CRC accelerators achieved better performance than traditional implementation. Based on the implementation, fully-adaptable CRC accelerator which eliminate the need for many non-adaptable CRC implementations is proposed. The accelerator has ability to process arbitrary number of input data and generates CRC for any known CRC standard, up to 65 bits of generator polynomial, during run-time. Further, we modify Table generation algorithm in order to decrease its space complexity from O(nm) to O(n). On Xilinx Virtex 6 LX550T board, the fully-adaptable accelerators occupy between 1 to 2% area to produce maximum of 289.8 Gbps at 283.1 MHz if BRAM is deployed, or between 1.6 - 14% of area for 418 Gbps at 408.9 MHz if tables are implemented in logic. Proposed architecture enables further expansion of throughput by increasing a number of input bits M processed at a time.

This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

In this paper, a robust cyclic ADC architecture with β-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder.

Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.