A Low-Power Microcontroller with Body-Tied SOI Technology

Hisakazu SATO; Yasuhiro NUNOMURA; Niichi ITOH; Koji NII; Kanako YOSHIDA; Hironobu ITO; Jingo NAKANISHI; Hidehiro TAKATA; Yasunobu NAKASE; Hiroshi MAKINO; Akira YAMADA; Takahiko ARAKAWA; Toru SHIMIZU; Yuichi HIRANO; Takashi IPPOSHI; Shuhei IWADE

A Low-Power Microcontroller with Body-Tied SOI Technology

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A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.563-570

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Hisakazu SATO, Yasuhiro NUNOMURA, Niichi ITOH, Koji NII, Kanako YOSHIDA, Hironobu ITO, Jingo NAKANISHI, Hidehiro TAKATA, Yasunobu NAKASE, Hiroshi MAKINO, Akira YAMADA, Takahiko ARAKAWA, Toru SHIMIZU, Yuichi HIRANO, Takashi IPPOSHI, Shuhei IWADE, "A Low-Power Microcontroller with Body-Tied SOI Technology" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 563-570, April 2004, doi: .
Abstract: A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e87-c_4_563/_p

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@ARTICLE{e87-c_4_563,
author={Hisakazu SATO, Yasuhiro NUNOMURA, Niichi ITOH, Koji NII, Kanako YOSHIDA, Hironobu ITO, Jingo NAKANISHI, Hidehiro TAKATA, Yasunobu NAKASE, Hiroshi MAKINO, Akira YAMADA, Takahiko ARAKAWA, Toru SHIMIZU, Yuichi HIRANO, Takashi IPPOSHI, Shuhei IWADE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Microcontroller with Body-Tied SOI Technology},
year={2004},
volume={E87-C},
number={4},
pages={563-570},
abstract={A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Low-Power Microcontroller with Body-Tied SOI Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 563
EP - 570
AU - Hisakazu SATO
AU - Yasuhiro NUNOMURA
AU - Niichi ITOH
AU - Koji NII
AU - Kanako YOSHIDA
AU - Hironobu ITO
AU - Jingo NAKANISHI
AU - Hidehiro TAKATA
AU - Yasunobu NAKASE
AU - Hiroshi MAKINO
AU - Akira YAMADA
AU - Takahiko ARAKAWA
AU - Toru SHIMIZU
AU - Yuichi HIRANO
AU - Takashi IPPOSHI
AU - Shuhei IWADE
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.
ER -