A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.

Detailed investigation has been made of a surface acoustic wave FM demodulator in which the phase difference between the input and output signals of a SAW delay device is detected. Total harmonic distortion of the audio output signal is measured to be 0.05%, a value comparable with best commercial practice with demodulators operating at a frequency deviation of 75 KHz with a center frequency of 10.7 MHz. Distortion mainly consists of evenorder harmonic components which are less objectionable to a listener than the odd-order harmonic components found in conventional high quality FM demodulators. Analysis shows that the distortion can be reduced reducing both the amplitude of the SAW spurious signals and the delay time difference between the spurious and main delay signals. The spurious SAW signals of concern included those from direct feed-through, triple-transit echoes, bulk waves, and edge reflections. Techniques for reducing or eliminating these are described. Calculated results are in fairly good agreement with experiment.

A dual-issue VLIW processor, running at 250 MHz, is enhanced with multimedia instructions for a sustained peak performance of 1000MOPS. The multimedia processor integrates 300 K transistors in an 8 mm2 core area and it is fabricated onto a 6 mm6. 2 mm chip with 32 kB instruction and 32 kB data RAMs in a 0. 3-micrometer, four-layer metal CMOS process. It consumes 1. 2 W at 2. 0 V running at 250 MHz. The VLIW processor achieves a speed-up of more than 4 times over a single-issue RISC for MPEG video block decoding. A decoder implemented on the multimedia processor with a small amount of dedicated hardware, such as the Huffman decoder and a DMA controller will decode the worst case 88 video block data in 754 cycles, leading to a real-time MPEG-2 system, video, and audio decoding system.

A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.

A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm 14.2 mm die with 11 million transistors.

Using Web-based content management systems such as Blog, an end user can easily publish User Generated Content (UGC). Although publishing of UGCs is easy, controlling access to them is a difficult problem for end users. Currently, most of Blog sites offer no access control mechanism, and even when it is available to users, it is not sufficient to control users who do not have an account at the site, not to mention that it cannot control accesses to content hosted by other UGC sites. In this paper, we propose new access control architecture for UGC, in which third party entities can offer access control mechanism to users independently of UGC hosting sites. With this architecture, a user can control accesses to his content that might be spread over many different UGC sites, regardless of whether those sites have access control mechanism or not. The key idea to separate access control mechanism from UGC sites is to apply cryptographic access control and we implemented the idea in such a way that it requires no modification to UGC sites and Web browsers. Our prototype implementation shows that the proposed access control architecture can be easily deployed in the current Web-based communication environment and it works quite well with popular Blog sites.

Linking schemes have been proposed assuming the model where the time-stamp issuer need not be trusted. However, in that environment, a fake chain attack and forward or backward dating attacks are still a residual risk in Time-Stamping services (TSS). In this paper, we propose a new time-stamping scheme that focuses on these problems. In our scheme, we use pseudonyms to prevent the time-stamp issuer from dating the time that the specific entity requests. Our scheme doesn't rely on only one trustworthy entity, and uses mutual communication between each entity. Two types of entities, server and clients without any trustworthy entities are configured in our system. The server provides an anonymous communication channel, but doesn't provide TSS, and the clients are not only time-stamp requesters but also issuers. So, when a client requests a time-stamp from the system, it is issued by one of the other clients.

In the context of resource isolation for network slicing, this paper introduces two resource allocation methods especially for the radio access network (RAN) part. Both methods can be implemented by slight modification of the ordinary packet scheduling algorithm such as the proportional fairness algorithm, and guarantee resource isolation by limiting the maximum number of resource blocks (RBs) allocated to each slice. Moreover, since both methods flexibly allocate RBs to the entire system bandwidth, there are cases in which the throughput performance is improved compared to when the system bandwidth is divided in a static manner, especially in a frequency selective channel environment. Numerical results show the superiority of these methods to dividing simply the system bandwidth in a static manner, and show the difference between the features of the methods in terms of the throughput performance of each slice.

Integrating a 243 MHz dual-issue RISC processor core with a small set of dedicated hardware can create a single chip system for real-time encoding and decoding for MPEG2 MP@ML (main profile at main level). A trade-off between software and dedicated hardware is very important to decide performance of the system. This paper evaluates several MPEG2 encoding and decoding systems, focusing on both chip area and power consumption. For MPEG2 encoding, a newly introduced hybrid approach includes the processor core and the dedicated hardware that performs the discrete cosine transform (DCT), the inverse DCT (IDCT), variable length encoding (VLC) and block loading process. The estimated area for the encoder, 23. 0 mm2 using a 0. 3-micrometer 1-poly 4-metal CMOS process, is 33% smaller than that of the dedicated hardware approach. The estimated power consumption for the encoder is 13% smaller than that of the dedicated hardware approach. The dual-issue RISC processor approach has the advantage of a small chip area, low power consumption and that of being very easy to program for multimedia applications.