An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-centered 6T SRAM cells.

A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.

This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.

This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm, and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

The susceptibility of a static random access memory (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90 nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.

A 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) memory cell has been proposed for field type of Magnetic Random Access Memory (MRAM). Proposed 1T-4MTJ memory cell array is achieved 44% higher density than that of conventional 1T-1MTJ thanks to the common access transistor structure in a 4-bit memory cell. A self-reference sensing scheme which can read out with write-back in four clock cycles has been also proposed. Furthermore, we add to estimate with considering sense amplifier variation and show 1T-4MTJ cell configuration is the best solution in IoT applications. A 1-Mbit MRAM test chip is designed and fabricated successfully using 130-nm CMOS process. By applying 1T-4MTJ high density cell and partially embedded wordline driver peripheral into the cell array, the 1-Mbit macro size is 4.04 mm2 which is 35.7% smaller than the conventional one. Measured data shows that the read access is 55 ns at 1.5 V typical supply voltage and 25C. Combining with conventional high-speed 1T-1MTJ caches and proposed high-density 1T-4MTJ user memories is an effective on-chip hierarchical non-volatile memory solution, being implemented for low-power MCUs and SoCs of IoT applications.

It is still an open problem to elucidate the scaling merits of an embedded SRAM with Low Operating Power (LOP) MOSFETs fabricated in 50, 70 and 100 nm CMOS technology nodes. Taking into account a realistic SRAM cell layout, we evaluated the parasitic capacitance of the bit line (BL) as well as the word line (WL) in each generation. By means of a 3-Dimensional (3D) interconnect simulator (Raphael), we focused on the scaling merit through a comparison of the simulated SRAM BL delay for each CMOS technology node. In this paper, we propose two kinds of original interconnect structure which modify ITRS (International Technology Roadmap for Semiconductors), and make it clear that the original interconnect structures with reduced gate overlap capacitance guarantee the scaling merits of SRAM cells fabricated with LOP MOSFETs in 50 and 70 nm CMOS technology nodes.