Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

Kei MATSUMOTO; Tetsuya HIROSE; Yuji OSAKI; Nobutaka KUROKI; Masahiro NUMA

doi:10.1587/transele.E94.C.1042

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

Kei MATSUMOTO, Tetsuya HIROSE, Yuji OSAKI, Nobutaka KUROKI, Masahiro NUMA

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We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.1042-1048

Publication Date: 2011/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.1042

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Kei MATSUMOTO, Tetsuya HIROSE, Yuji OSAKI, Nobutaka KUROKI, Masahiro NUMA, "Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 6, pp. 1042-1048, June 2011, doi: 10.1587/transele.E94.C.1042.
Abstract: We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1042/_p

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@ARTICLE{e94-c_6_1042,
author={Kei MATSUMOTO, Tetsuya HIROSE, Yuji OSAKI, Nobutaka KUROKI, Masahiro NUMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit},
year={2011},
volume={E94-C},
number={6},
pages={1042-1048},
abstract={We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.},
keywords={},
doi={10.1587/transele.E94.C.1042},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1042
EP - 1048
AU - Kei MATSUMOTO
AU - Tetsuya HIROSE
AU - Yuji OSAKI
AU - Nobutaka KUROKI
AU - Masahiro NUMA
PY - 2011
DO - 10.1587/transele.E94.C.1042
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.
ER -