This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.

This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.

This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The proposed ROSC employs a compensation circuit of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable, and 32-kHz oscillation clock frequency without increasing power dissipation by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-$mu$m CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55,kHz with low power dissipation of 472,nW at 1.8-V power supply. Measured line regulation and temperature coefficient were 1.1%/V and 120,ppm/$^{circ}$C, respectively.

A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by not only offset voltage, but also delay time. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66kHz. The current dissipation was 320nA at 1.0-V power supply. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

Advanced nanometer circuits are susceptible to errors caused by process, voltage, and temperature (PVT) variations or due to a single event upset (SEU). State-of-the-art design-for-variability (DFV)-aware flip-flops (FFs) suffer from their area and timing overheads. By utilizing C-element modules, two types of FFs are proposed for error detection and error correction.

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-µm standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212 kHz can remain by using compensation in the range from 5.26 to 19.2 kHz.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

Adaptive voltage management (AVM) scheme is proposed for worst-caseless lower voltage SoC design. The AVM scheme detects the temperature accurately by using two oscillators with different temperature characteristics, and sets supply voltage most suitable with a table look-up method corresponding to the process variation. Also, the AVM can supply the stable voltage with a local shift type regulator even at lower voltage. Thereby, this supply-voltage control system considering PVT variations can control the internal voltage corresponding to process and temperature variations and can realize a wide-operating-margin, DFM function for low voltage SoC. The experimental chip is fabricated on a 90 nm CMOS process, and it was confirmed that the proposed architecture controls the voltage accurately and has a wide operating margin at a lower voltage.

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.