1-2hit |
Yasushi ITOH Masatoshi NII Norio TAKEUCHI Yoshihiro TSUKAHARA Hidetoshi KUREBAYASHI
This paper describes the design, fabrication, and performance of a C- to Ku-band 2 W balanced amplifier multi-chip module employing an MMIC/Super-MIC/MIC configuration. In this module, single-ended amplifiers, quadrature couplers, and pulsed-drive circuits are fabricated on MMICs, Super-MICs, and MICs, respectively, which show different features in fabrication, performance, size, and cost. With the use of the distinguished features of MMICs, Super-MICs, and MICs, the multi-chip module with high performance, small size, and low cost has been achieved. The MMIC/Super-MIC/MIC-combined module would be a candidate for a variety of multi-chip modules with stringent requirements for performance, size, and cost.
Kazutomi MORI Kazuhisa YAMAUCHI Masatoshi NAKAYAMA Yasushi ITOH Tadashi TAKAGI Hidetoshi KUREBAYASHI
This paper describes the design, fabrication, and performance of a GaAs FET linearizer with a large source inductance, focusing mainly on (a) a mechanism of positive gain and negative phase deviations for input power, (b) stability considerations, and (c) a dependence on load impedance. In addition, in an application to the linearized amplifier, it is shown that an improvement can be achieved for adjacent channel leakage power (ACP) and third order intermodulation distortion (IM3) with the use of the linearizer.