This paper presents a miniaturized dual-mode Doherty PA module applicable for an HPSK signal and an OFDM 64-QAM signal. Dual-mode operation with identical hardware is realized by introducing a bias switching technique, which changes bias conditions of amplifiers according to transmission signals, and employing dual-mode matching circuits, which are designed based on the results of load-pull measurements using an HPSK signal and an OFDM 64-QAM signal. The Doherty PA module consists of a Doherty stage and a gain stage. Two GaAs-HBTs for a Doherty stage and one GaAs-HBT for a gain stage are integrated onto a 1 mm-square single GaAs-MMIC. In the HPSK mode, maximum output power of 26.7 dBm, power added efficiency (PAE) of 41%, and power gain of 27 dB are obtained in the condition that adjacent channel leakage power ratio (ACLR) is under -38 dBc. In the OFDM 64-QAM mode, maximum output power of 21.0 dBm, PAE of 27%, and power gain of 28 dB are obtained under EVM < 3.0%. This is the first multi-mode Doherty PA module suitable for multi peak to average power ratio (PAPR) signals.

Recently, dynamic power supply voltage techniques, such as an Envelope Elimination and Restoration power amplifier (EER-PA) or Envelope-Tracking Power amplifier (ET-PA), have been attracting much attention because they can maintain high efficiency in large back-off region [1]-[6]. The dynamic power supply voltage techniques cause strong nonlinearity compared to a conventional power amplifier, hence a memoryless Digital Predistortion (DPD) technique is indispensable for these efficiency enhancement techniques. However, the performance of the memoryless DPD is degraded due to the frequency response of the envelope amplifier in the dynamic power supply voltage techniques [7]-[9]. In this paper, we clarify the degradation mechanisms of the memoryless DPD for the EER-PA due to the frequency response of the envelope amplifier based on the results of two-tone tests, and propose an analytical model for improving the performance of the memoryless DPD developed for the EER-PA. In addition, a prototype EER-PA is developed and we demonstrate that the residual distortion of the developed EER-PA with conventional memoryless DPD algorithm is compensated by the new algorithm based on the proposed analytical model. In the two-tone test, third-order intermodulation distortion (IMD3) with a tone spacing from 100 kHz to 4 MHz is improvement by up to 25 dB by the memoryless DPD algorithm based on the proposed model. Measured adjacent channel leakage power ratio (ACPR) of the developed EER-PA is improved from -22.5 dBc to -42.5 dBc in the OFDM signal test with 1.08 MHz bandwidth.

A 0.15 µm T-shaped gate AlInAs/InGaAs high electron mobility transistor (HEMT) with an excellent RF performance has been developed using selective wet gate recess etching. The gate recess is formed by a pH-adjusted citric acid/NH4OH/H2O2 mixture with an etching selectivity of more than 30 for InGaAs over AlInAs. The standard deviation of saturation drain current (Idss) is as small as 3.2 mA for an average Idss of 47 mA on a 3 inch diameter InP wafer. The etching time for recess formation is optimized and an ft of 130 GHz and an MSG of 10 dB at 60 GHz are obtained. The extremely low minimum noise figure (Fmin) of 0.9 dB with an associated gain (Ga) of 7.0 dB has been achieved at 60 GHz for a SiON-passivated device. This noise performance is comparable to the lowest value of Fmin ever reported for an AlInAs/InGaAs HEMT with a passivation film.

A Q-band high gain and low noise Variable Gain Amplifier (VGA) module using dual gate AlGaAs/InGaAs pseudomorphic HEMTs has been developed. The dual gate HEMT can be fabricated by the same process of the single gate HEMT which has the gate length of 0.15 µm. The Q-band VGA module consists of a 1-stage low noise amplifier (LNA) MMIC using a single gate HEMT and a 2-stage VGA MMIC using dual gate HEMTs. During the design, an accurate noise modeling is introduced to achieve low noise performance. A fully passivated film is employed to achieve reliability. The VGA module has a gain of more than 20 dB from 41 GHz to 52 GHz and a maximum gain of 24.5 dB at 50 GHz. A gain control range of more than 30 dB is achieved in the same frequency range. A phase deviation is less than 10 degrees in 10 dB gain control range. A minimum noise figure of 1.8 dB with an associated gain of 22 dB is achieved at 43 GHz and the noise figure is less than 2.5 dB with associated gain of more than 20 dB from 41 GHz to 46 GHz when biased for low noise figure. This performance is comparable with the best data ever reported for LNAs at Q-band including both GaAs based HEMTs and InP based HEMTs.

An ultra low noise 50-GHz-Band amplifier (LNA) MMIC has been developed using an AlGaAs/InGaAs pseudomorphic HEMT. A noise figure of 1.8 dB with an associated gain of 8.1 dB is achieved at 50 GHz. The noise figure is less than 2.0 dB from 50 GHz to 52.5 GHz. This is the state-of-the-art noise figure for low noise amplifiers around 50 GHz. The success of this LNA development came from the excellent HEMT and MMIC technologies and the accurate modeling of active and passive elements. Good agreement between measured and simulated data over the band from 40 GHz to 60 GHz is obtained.

Millimeter-wave monolithic low noise amplifier modules using 0.15 µm AlGaAs/InGaAs/GaAs pseudomorphic HEMTs have been developed at V- and W-bands for the Advanced Microwave Scanning Radiometer. To achieve low noise and high gain of V-band single-stage and W-band two-stage monolithic amplifiers, a reactive matching method is employed in the design of input noise matching and output gain matching circuits based on the results of on-carrier S-parameter measurements up to 50 GHz and noise parameter measurements at 60 and 90 GHz. A V-band four-stage monolithic amplifier module has been mounted on a hermetically-sealed package with microstrip interface and has achieved a noise figure of 3 dB with a gain of 42.2 dB at 51 GHz. A W-band six-stage amplifier module has been mounted on a hermetically-sealed package with waveguide interface and has achieved a noise figure of 4.3 dB with a gain of 28.1 dB at 91 GHz. These results represent the best noise figure performance ever achieved by multi-stage monolithic low-noise amplifier modules.

A novel millimeter-wave on-wafer CAT(Computer-Aided-Testing ) system has been developed for measurement of S-parameters and NF ( Noise figure ). For the S-parameter test system, we have developed a holder setup and installed it in a semi-automatic wafer prober so that the waveguide-based T/R module can be directly connected to a probe-head through fixed waveguides, which feature low insertion loss of less than 2 dB, from 75 GHz to 98 GHz. The accuracy of the developed test system was confirmed by measuring, with this system, a co-planar offset short pattern then comparing measured and simulated results. A good agreement between the measured and calculated, in both return loss and return phase successfully demonstrated the superiority of the system. A W-band NF test system with a system noise of less than 8 dB has been also developed to provide an on-wafer NF measurement capability with an accuracy of 0.3 dB. These S-parameter and NF test systems possess great advantages to achieve high-speed automatic MMIC testing up to W-band.

This paper describes numerical analyses of resistive mixer operation, followed by measured performances of a V-band (50 - 75 GHz) monolithic InP HEMT resistive mixer operable with a very low LO power. Our model assumes that the channel conductance of the InP HEMT can be described by three linear functions according to the applied gate voltage. The calculated results obtained with the model have shown that the LO power level required for mixer operation is determined by the gate bias voltage and that a device with abrupt conductance shifts is suited to low LO power operation for a resistive mixer. It is also shown that conversion loss saturation of a resistive mixer is caused by its channel conductance saturation. A V-band monolithic resistive mixer has been designed and fabricated using Coplanar Waveguides (CPW) and a 0.15 mm InP HEMT with abrupt channel shifts. Good agreement between measured and simulated conversion losses are obtained. A minimum conversion loss of 8.4 dB is achieved at the 55 GHz RF-frequency and the -2 dBm LO power. It also exhibits an excellent IF output linearity to allow the 1 dB compression RF input level to be comparable with LO power, indicating good intermodulation performance. It is demonstrated that the proposed simple model of the channel conductance can easily calculate conversion characteristics of a resistive mixer with high accuracy.

Recently, the Doherty amplifier technique has been the focus of attention not only for base stations but also for mobile terminals because of its high power-added efficiency in the large back-off region. In this paper, we present a miniaturized Doherty power amplifier (PA) module for W-CDMA mobile terminals. The developed Doherty PA module consists of a 4-mm-square ceramic substrate (4.0 mm4.0 mm1.5 mm, alumina, dielectric constant = 8.8), a 1-mm-square GaAs MMIC (1.0 mm1.0 mm0.1 mm), and 0603-size SMD passive components. To miniaturize the module size, the optimal designed quarter-wavelength transmission lines, which are used for impedance conversion for carrier amplifier output and phase compensation for peak amplifier input, are embedded in the ceramic module substrate. Two GaAs HBTs for a carrier amplifier and a peak amplifier and base bias circuits for each amplifier are integrated onto a single-chip GaAs MMIC. Measurement results at 1950 MHz in a W-CDMA uplink signal indicate that 27 dBm of the maximum output power, 45% of the power-added efficiency (PAE), 11 dB of power gain, and 43% of PAE at 6 dB back-off, i.e. 24 dBm output power, are obtained with the developed Doherty PA. In other words, the PAE is improved from the theoretical PAE of a conventional class B amplifier, namely, from 23% to 43%. This is the smallest Doherty amplifier developed in the form of a module for mobile terminals.