This paper describes the reliability on recess type T-shaped gate HEMTs and their major failure mechanism investigated by accelerated life tests and following failure analysis. In this study, high temperature storage tests with a DC bias condition have been conducted on three different recess depths of 100, 125, and 150 nm. The results have clarified that the shallow recess devices of under 125 nm depth have no degration in minimum noise figure Fmin or gain Ga characteristics, indicating that standard HEMT devices, whose recess depth is chosen to be far under 125 nm, possess a sufficient reliability level. However, the devices with deep recess of 150 nm have shown degradation in both Fmin and Ga. Precise failure analyses including SEM observation and von Mises stress simulation have firstly revealed that the main failure mode in deeply recessed T-shaped gate HEMTs is increase in gate electrode's parasitic resistance Rg, which is caused by separation of "head" and "stem" parts of the T-shaped gate electrode due to thermo-mechanical stress concentration.

A novel nonlinear analysis method of high power amplifier instability has been developed. This analysis method deals with a loop oscillation in a closed loop circuit and presents the conditions for oscillation under large-signal operation by taking account of mixing effect of FETs. Applying this analysis to the high power amplifier instability that an output power for the fundamental wave (f0-wave) decreases at some compression point where a half of the fundamental wave (f0/2-wave) is observed, it has been found that this instability is caused by an f0/2 loop oscillation. In addition, it has been verified by analysis and experiment that the oscillation can be removed by employing an isolation resistor in a closed loop circuit.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

A refection type and loaded-line type phase shifter switching multi phase-states has been described. This novel phase shifter circuit is constructed by adding switching FETs to a conventional 2-phase-state phase shifter. A conventional 3 bit phase shifter can be replaced by this type of phase shifter. The total chip size is reduced to 2/3. This paper reports on the design, fabrication, and performance of the novel reflection-type and loaded-line-type phase shifter MMICs.

Millimeter-wave monolithic low noise amplifier modules using 0.15 µm AlGaAs/InGaAs/GaAs pseudomorphic HEMTs have been developed at V- and W-bands for the Advanced Microwave Scanning Radiometer. To achieve low noise and high gain of V-band single-stage and W-band two-stage monolithic amplifiers, a reactive matching method is employed in the design of input noise matching and output gain matching circuits based on the results of on-carrier S-parameter measurements up to 50 GHz and noise parameter measurements at 60 and 90 GHz. A V-band four-stage monolithic amplifier module has been mounted on a hermetically-sealed package with microstrip interface and has achieved a noise figure of 3 dB with a gain of 42.2 dB at 51 GHz. A W-band six-stage amplifier module has been mounted on a hermetically-sealed package with waveguide interface and has achieved a noise figure of 4.3 dB with a gain of 28.1 dB at 91 GHz. These results represent the best noise figure performance ever achieved by multi-stage monolithic low-noise amplifier modules.

A wideband monolithic lossy match power amplifier having an LPF/HPF-combined interstage network has been developed. As an interstage network, it employs an LPF (Low-Pass Filter) including FET's drain capacitance, an HPF (High-Pass Filter) comprised of a dc blocking capacitor and a drain bias circuit, and a constant-resistance network for wideband impedance matching and transformation. With the use of this interstage network, a wide bandwidth of 6 to 16.5 GHz and an output power of 30.40.9 dBm have been achieved.

A microwave waveform measurement system below 18 GHz was developed and verified with a conventional RF measurement. The current and voltage RF waveforms of AlGaAs HBTs at the fundamental frequency of 1 GHz were directly measured with the system. A new direct method of sweeping and measuring dynamic RF load lines is proposed to measure the operating limits of the device. The maximum operating region was experimentally investigated with this method. The limits with a small input power are found to come from thermal runaway and the avalanche breakdown of the device. With a large input power, the HBT was found to operate beyond the DC limit of thermal runaway. The base ballasting resistance was also found to enhance large signal operating limits beyond those expected from the conventional DC theory.

This paper describes numerical analyses of resistive mixer operation, followed by measured performances of a V-band (50 - 75 GHz) monolithic InP HEMT resistive mixer operable with a very low LO power. Our model assumes that the channel conductance of the InP HEMT can be described by three linear functions according to the applied gate voltage. The calculated results obtained with the model have shown that the LO power level required for mixer operation is determined by the gate bias voltage and that a device with abrupt conductance shifts is suited to low LO power operation for a resistive mixer. It is also shown that conversion loss saturation of a resistive mixer is caused by its channel conductance saturation. A V-band monolithic resistive mixer has been designed and fabricated using Coplanar Waveguides (CPW) and a 0.15 mm InP HEMT with abrupt channel shifts. Good agreement between measured and simulated conversion losses are obtained. A minimum conversion loss of 8.4 dB is achieved at the 55 GHz RF-frequency and the -2 dBm LO power. It also exhibits an excellent IF output linearity to allow the 1 dB compression RF input level to be comparable with LO power, indicating good intermodulation performance. It is demonstrated that the proposed simple model of the channel conductance can easily calculate conversion characteristics of a resistive mixer with high accuracy.

Focused Ion Beam (FIB) trimming techniques for circuit optimization for GaAs MMICs by adjusting the parameters of IC components such as resistors, capacitors, microstrip lines, and FETs have been developed. The adjustment is performed by etching of the components and depositing of metal films for micro-strip lines. This technology turned out to be in need of only half a day to optimize the circuit pattern without any further wafer processes, while a conventional method that is comprised of revising mask pattern and following several cycles of wafer process has needed 0.5-1.0 year requiring huge amount of development cost. This technology has been successfully applied to optimization of an X-band low dissipation current single stage MMIC amplifier, and has shown its great feasibility for shortening the turn around time.

Air-bridge metal interconnection technology is used for upper level power supply line interconnections in GaAs LSI's to reduce the signal propagation delay time. This technology reduces both parasitic capacitance between the signal line and the power supply line, and propagation delay in the signal line to about 10% and about 50%, respectively, compared to conventional 3-level interconnections without air-bridges. Under standard load conditions (FI=FO=2, length of load line=2 mm), the air-bridge technique leads to gate propagation delays which are about 60% of those in conventional interconnections. We fabricated 2.1-k gate Gate Arrays and 4-kb SRAM's using the air-bridge structure to interconnect power supply lines. For a Gate Array with 0.7 µm gate Buried P-layer Lightly Doped Drain (BPLDD) FET's, the typical gate propagation delay under standard load conditions was about 110 ps with a dissipation power of 1.4 mW/gate. SRAM's with 05 µm gate BPLDD's had typical access time (tacc) of 1.5 ns with a dissipation power of 700 mW/chip.