Monolithically integrated four-channel distributed feedback (DFB) laser array has been fabricated by metal organic vapor phase epitaxy (MOVPE) selective area growth for 1.55 µm coarse-wavelength division multiplexing (CWDM) systems. Wide-stripe MOVPE selective area growth and electron-beam lithography are used to obtain wide CWDM channel spacing of 20 nm. Compared to hybrid integration of discrete lasers, monolithic integration of laser array on a single substrate greatly simplifies device alignment and packaging process.

Linear codes with a few weights have many applications in secret sharing schemes, authentication codes, association schemes and strongly regular graphs, and they are also of importance in consumer electronics, communications and data storage systems. In this paper, based on the theory of defining sets, we present a class of five-weight linear codes over $mathbb{F}_p$(p is an odd prime), which include an almost optimal code with respect to the Griesmer bound. Then, we use exponential sums to determine the weight distribution.

Simulation and fabrication results on back-illuminated 4-channel photodiode (PD) array with a self-aligned micro ball lens are described. The channel pitch and diameter of each photosensitive area are 250 µm and 40 µm, respectively. Measured photocurrent is 1.92 times larger than that without a lens. Alignment tolerance between the single mode fiber (SMF) optical axis and the photodiode is improved from 21.2 µm to 42.7 µm. Moreover, the separation tolerance between the fiber and the lens is 210.5 µm. These large tolerances agree with simulation results, demonstrating that the device configuration is suitable for receivers for multi-channel inter-connection. Frequency response and inter-channel cross talk are also discussed.

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.

This letter proposes a power amplifier (PA) with compact matching network. This structure is a parallel dual radial microstrip line in the output matching network branch. The input impedance expression based on the structure is deduced through theoretical analysis, and the load impedance that satisfies the class EFJ PA is obtained through the impedance expression. Compared with the traditional design method, this design method is simple and novel, and the structure is more compact. In order to further improve efficiency and expand bandwidth, the input matching network adopts a stepped impedance matching method. In order to verify the correctness of the design, a broadband high-efficiency PA was designed using GaN HEMT CGH40010F. The test results show that the drain efficiency is 61%-71% in the frequency band 1.4-3.8GHz, the saturated output power is 40.3-41.8dBm, and the size is 53×47mm2.

For the problem of Indoor Home Scene Classification, this paper proposes the BOW Model of Local Feature Information Gain. The experimental results show that not only the performance is improved but also the computation is reduced. Consequently this method out performs the state-of-the-art approach.

To address the challenge of target signals being completely submerged by ionospheric clutter during typhoon passages, this letter proposes a chaotic detection method for target signals in the background of ionospheric noise under typhoon excitation. Experimental results demonstrate the effectiveness of the proposed method in detecting target signals with harmonic characteristics from strong ionospheric clutter during typhoon passages.

This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.

We propose to use clustered interference alignment for the situation where the backhaul link capacity is limited and the base station is cache-enabled given MIMO interference channels, when the number of Tx-Rx pairs exceeds the feasibility constraint of interference alignment. We optimize clustering with the soft cluster size constraint algorithm by adding a cluster size balancing process. In addition, the CSI overhead is quantified as a system performance indicator along with the average throughput. Simulation results show that cluster size balancing algorithm generates clusters that are more balanced as well as attaining higher long-term throughput than the soft cluster size constraint algorithm. The long-term throughput is further improved under high SNR by reallocating the capacity of the backhaul links based on the clustering results.