In the field of Factory Automation (FA), process control, and Supervisory Control and Data Acquisition (SCADA), an analog data acquisition system using isolation transformers is commonly used to measure and record analog signals through isolated inputs. In order to improve the input precision of the acquisition system, circuit techniques and a design method of the analog frontend circuit with the signal transformers are proposed in this paper. A circuit technique to compensate for the droop of the pulse signal due to the characteristics of the signal transformer is employed. Also, a numerical analysis of a non-linear circuit equation, which represents a behavior of the core saturation of the signal transformer, is performed in order to determine the parameters of the circuit. Using a small signal transformer, dedicatedly developed for this acquisition system, the performance of the precision achieved for the linearity error is experimentally confirmed within +0.0204%/-0.0215%.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

Over 100 Gbit/s/ch high-speed optical transmission is required to achieve the high capacity networks that can meet future demands. The coherent receiver, which is expected to yield high frequency utilization, is a promising means of achieving such high-speed transmission. However, it requires a high-speed Analog to Digital Converter (ADC) because the received signal bandwidth would be over several tens or hundreds of GHz. To solve this problem, we propose a band-divided receiver structure for wideband optical signals. In the receiver, received wideband signals are divided into a number of narrow band signals without any guard band. We develop a band-divided receiver prototype and evaluate it in an experiment. In addition, we develop a real-time OFDM demodulator on an FPGA board that implements 1.5 GS/s ADCs. We demonstrate that the band-divided receiver prototype with its real-time OFDM demodulator and 1.5 GS/s ADC can demodulate single polarization 12 Gbit/s OFDM signals in real-time.

We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

Based on the theoretical analysis of literature, saturation in measured signal of active noise control (ANC) systems will degrade the convergence speed. However, the experiments show that the saturated input signal can speed up the convergence of the narrow-band ANC systems. This paper intends to remodel the saturation effects for feedforward and feedback ANC systems. Combining the action of analog-to-digital converters (ADC), the mathematical expression and block diagrams are proposed to model the saturation effects in the practical ANC systems. The derivation and simulation results show that since the saturation is able to amplify the principle component of signal, the convergence would be speeded up.

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

The analog IC technology, might sound old-fashioned, is still important for the future wireless systems such as 4G cellular phone systems, broadband wireless networkings, and wireless sensor networkings. The analog features and issues of the scaled CMOS transistor, the basic issue and the technology trend for the ADC as an important building block of wires systems, and the feature of the digital RF architecture proposed recently are reviewed and discussed. Higher speed and lower power consumption are expected for low SNR systems along with the further technology scaling. However, the high SNR system is not realized easily due to a decrease of signal voltage. One of the important technology trends is the digitalization of RF signal to realize the system flexibility, robustness, area shrinking, and TAT shortening.

We present a method of extracting the digital inphase (I) and quadrature (Q) components from oversampled bandpass signals using narrow-band bandpass Hilbert transformers. Down-conversion of the digitized IF signals to baseband and reduction of the quantization noise are accomplished by the multistage decimator with the complex coefficient bandpass digital filters (BPFs), which construct the bandpass Hilbert transformers. Most of the complex coefficient BPFs in the multistage decimator can be replaced with the lowpass filters (LPFs) under some conditions, which reduces computational burden. We evaluate the signal to quantization noise ratio of the I and Q components for the sinusoidal input by computer simulation. Simulation results show that the equivalent amplitude resolution of the I and Q components can be increased by 3 bits in comparison with non-oversampling case.