We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on the gm/ID methodology. Thermometer coder with the dynamic element matching and ΔΣ modulator are implemented for the frequency tuning. High frequency resolution is achieved by using the ΔΣ modulator. The ΔΣ-modulator-based LC-DCO implemented in a 130-nm CMOS technology has achieved the phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with the tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 700 µW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm2 and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

This paper considers a simple type of Dynamic Element Matching (DEM), Clocked Averaging (CLA) method referred to as one-element-shifting (OES) and its effectiveness for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique discussed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the other published DEM methods. With this OES, a 3rd order, 10 MHz bandwidth continuous-time DSM is implemented in 90 nm CMOS process. The measured SFDR attains 83 dB for a 10 MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10 dB.

This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10 dB improvement of THD+N performance under -50 dB amplitude input signal, compared to the case without the proposed technique.

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.