Katsuhiko YAMAMOTO Tomoji SUGAI Koichi TANAKA
A 10-kW (53V/200A), forced-air-cooled DC-DC converter has been developed for fuel cell systems. This converter uses new high-voltage bipolar-mode static induction transistors (BSIT), a new driving method, a zero-voltage-switched pulse-width-modulation technique, and a new litz wire with low AC resistance. It weighs only 16.5kg, has a volume of 26,000cm3, operates at 40kHz, and has a power conversion efficiency of about 95%. The power loss of this converter is 20% less than that of conventional natural-air-cooled DC-DC converters, and the power density is 3 times as high.
Yuu WATANABE Yasuhiro NAKASHA Kenji IMANISHI Masahiko TAKIKAWA
We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.
Yasuo NARA Manabu DEURA Ken-ichi GOTO Tatsuya YAMAZAKI Tetsu FUKANO Toshihiro SUGII
This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.
Takaaki YAGI You-Wen YI Mitsuchika SAITOH Nobuo MIKOSHIBA
A novel effective channel length extraction method has been developed, which utilizes the difference between the local threshold voltage of channel region and that of external region. In this method, the dependence of external resistance on Vg is taken into account, and it is not necessary to extract Vth. It is found that the external resistance can be approximated as the linear function of Vg with Vg around Vth. For a 0.4 µm gate length LDD MOSFET, the accuracy and resolution are estimated to be less than 0.02 µm and 0.003 µm, respectively.
Terutaka TAMAI Tetsushi KAWANO
On the surface of contacts which are exposed to the atmosphere, the reaction with gases in the atmosphere produces contaminant films including oxides. The contact reliability is degraded by the contaminant films. Humidity in the atmospheric environment also influences on the surface of contacts. However, influence of humidity on the surface has not been clarified. In the present paper, influence of humidity on the Cu surface and the oxides (CuO + Cu2O) on it were studied with respect to the thickness of the oxide film and contact resistance characteristics both for static and for sliding contacts. The thickness was measured by ellipsometric analysis. Topographic image affected by humidification was also observed by scanning tunneling microscope (STM). In the atmospheric environment, the clean surface of Cu was found to oxidize with fluctuations of the thickness for lapse of exposure time due to the fluctuations of the humidity. It was also found that the thickness of the oxide film decreases immediately after the humidification, and increases under dehumidification. Changes in contact resistance affected by humidity was corresponding to the change in the film thickness. Immediately after humidification contact resistance decreased, and increased with dehumidification both for static and for sliding contacts. For the mechanism of the influence of humidity on the oxide, chemical reduction of hydrogen generated by decomposition of the absorbed water molecule (H2O) was derived. The clean Cu surface was oxidized by oxygen due to absorbed water molecule and atmosphere.
Isao MINOWA Mitsunobu NAKAMURA
Plating is applied to protect contact surfaces of contact devices such as switch, relay and connector from contaminations of oxidization and sulfuration etc. Furthermore it is known that the contact resistance can be reduced when there exist plated layers on the contact surfaces which have enough thickness and low resistivity compared with substratum materials. In this paper, contact resistance between plated conductors are calculated using three dimensional finite element method. Similariry, current density distribution in a contact spot with various resistivity of plated layers are shown and relative conductance depends on the contact area fraction with thickness of plated layers are presented.
Composite materials of solid lubricants, such as graphite, MoS2, WS2, etc., and metals are being used as the sliding electrical contacts. However, few reports have so far been presented on the detailed characteristics of such composite materials. It is shown in this report that contact resistance and coefficient of friction of the sliding contact of the composite material of Cu-Nb system against Cu were higher than those of the sliding contact of the composite material of Cu-Sn system against Cu. It was, further, found that composite materials of Cu-Sn system were superior to those of Cu-Nb system being both contact resistances and coefficients of friction lowered. At the same time, it was found that performances of composite materials of Cu-Sn alloy base containing exclusively WS2 were superior to those containing both WS2 and MoS2. It was, therefore, suggested that proper samples suitable for the service conditions should be selected from the composite materials of Cu-Sn system which contain exclusively WS2 for the practical applications.
Zhuan-Ke CHEN Keisuke ARAI Koichiro SAWA
The former experimental results have already shown that it is oxide films formed on contact surface causing the contact resistance to degrade in dc. breaking arcs for Ag and Pd materials. In order to understand the detailed information about it, the experiments are performed to break dc. inductive load at 20 V, 0.5 A and 1.0 A in nitrogen gas with different oxygen concentrations. The contact surface morphology and surface contamination are evaluated by SEM and AES, respectively. The tested results demonstrate that, for Ag contact, the severe oxidation occurs with increasing oxygen concentration, and the critical value of oxygen concentration is found to be about 10% and 5% in 0.5 A and 1.0 A, respectively, above those values the contact resistance degrades due to the oxide films formed on the contact surface, especially on the anode surface. While, for Pd contacts, a remarkable contact resistance degradation is not found even at 1.0 A in oxigen. Evidence shows that the arc duration, in particular the gaseous phase arc duration affects the anode oxidation, which in turn causes the significant fluctuation of contact resistance.
Hitoshi NISHIYAMA Mitsunobu NAKAMURA Isao MINOWA
The electric or electronic circuits have many contact devices such as relay and switch. The contact between two nominally conducting flat surface has a lot of micro contact spots. The constriction resistance of the contact is known to determine the sum of the parallel resistance of the micro contacts and the interaction of them. The constriction resistance of two circular conducting spots was approximately formulated by Greenwood. This formulation shows that the interacted resistance of two circular spots is in inverse proportion to the distance between two conducting spots. It was known that this effect is introduced by the interaction between two conducting spots. However, the condition of interaction in the spots is not clear. Calculating the current density distribution in the spots is important to clarify the condition of interaction. The numerical analysis is very suitable to calculate the current density in the spots. In the fundamental case of the computation of the current density the boundary element method (BEM) is more efficient and accurate than that of the finite element method (FEM) because the boundary condition at the infinite is naturally satisfied and is not required a great number of the element in a wide space. In this paper the current density in the square spots is computed by the BEM. As the distance between two conducting spots becomes small, the current density in the two spots decreases. It becomes clear that the constriction resistance of conducting spots is increased by this effect. The decrease of current density by interaction is not uniformly, that at the near location to the opposite spot is larger than that at the far location in the same spot. In this paper the constriction resistance of two conducting spots is also considered. It was known that the constriction resistance of one conducting spot is not influenced by the form of spot very much. However, that of two conducting spots is not clear. The constriction resistance of two square spots is also computed by the BEM. The computed values of the constriction resistance of two square spots are compared with that of two circular spots by Greenwood's formulation and other results. As the result, it is clear that they have the considerable discrepancy. However, the trend of the variations is almost agree each other.
Hideki IWATA Toshio OHYA Shoji MITSUISHI Hiroki MARUYAMA
In this paper, the relationship between contact materials and sticking characteristics, and stability of contact resistance to obtain excellent contacts for telecommunication relays, is studied. The contact switching current for telecommunication relay is low. Moreover, contact force and opening force in these relay are respectively several mN. Nine kinds of contact materials are selected as a experimental factor. They are Ag, Ag-Ni (Ni: 0.03 to 20%), Ag-Cu 10%, Ag-Pd 60% and Pd-Ru 10%, and are overlaid with gold except Pd-Ru 10%. In this study, contact life tests on a commercial ultra-miniature telecommunication relay by mounting above-mentioned contacts are conducted. The sticking and the contact resistance are monitored at each switching operation in the contact life test. After the life test, the contact surfaces are observed, and the depth of crater, the height of pip and projected concave area are measured, then the relationship between the sticking morphologies and the composition of each material are studied. As the result of this study, the contact sticking of telecommunication rely is assumed to be the result of mechanical locking, and the effects of the Ni content in the Ag-Ni contacts is clarified. Moreover, it is confirmed that the effects of opening force on the sticking characteristics are remarkable.
Gate-controlled negative differential resistance (NDR) due to interband tunneling has been observed at room temperature in a Surface Tunnel Transistor (STT). The STT consists of a highly degenerate p+-drain, an n+-doped channel with an insulated gate, and an n+-source connected to the channel. To demonstrate application as a functional device, a bistable circuit consisting of only one STT and one load resistor was organized and its operation was confirmed. The obtained valley current in the NDR characteristics of the STT, however, is relatively large and limits the device performance. In order to clarify the origin of the valley current, we fabricated p+-n+ tunnel diodes in which growth interruption was done at the pn junction, and investigated the dependence of the NDR characteristics on both the impurity concentration at the regrown interface and the temperature. These measurements indicate that the valley current is mainly caused by the excess tunneling current through traps formed by the residual oxygen at the regrown interface.
A convenient method for determining emitter and base resistances from small signal measurements has been developed. This method is based on Neugroschel's method, but the frequency has been varied instead of varying β0. It is demonstrated that the base resistance was successfully extracted. The extracted emitter resistance depended on the collector current because of the difference between the exact gm value and the approximated one, IC/VT. It has also been shown that the proposed method is more robust than the conventional impedance-circle method even when cross-talk occurs.
Ken-ichi GOTO Tatsuya YAMAZAKI Yasuo NARA Tetsu FUKANO Toshihiro SUGII Yoshihiro ARIMOTO Takashi ITO
Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi2 takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800 for 30 seconds, while it does not occur in TiSi2 gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.
Tatsuya OMORI Ken'ichiro YASHIRO Sumio OHKAWA
An exact analysis for magnetostatic surface wave excitation by a single microstrip is presented. Conventional approaches for such an excitation problem do not explain experimental results in a reasonable manner. The theory proposed here explains radiation resistances obtained by experiments, owing to having considered the edge conditions and an expansion form of excitation current on the microstrip properly.
Tsutomu MATSUSHITA Teruyoshi MIHARA Masakatsu HOSHI Minoru AOYAGI
We have developed new DMOS FET (DMOS) and intelligent power devices (IPD) specified for automotive load driving. Their features are extra-high surge immunity and low on-resistance. MOS power semiconductor devices are the most suitable for driving high speed and large current loads in future car electronics, but their high cost is the main obstacle preventing their implementation. To cut the total system cost, we have tried to enhance surge immunity of power semiconductor devices, at the same time reducing ON resistance, which enables us to omit external protection. Enhanced avalanche power dissipation also enables us to lower the breakdown voltage of the device, which also brings lower on-resistance. The drain to source avalanche immunity of vertical type DMOS (VDMOS) has been sharply improved by using the parasitic PN junction of the channel diffusion region as the cellular zener diode. Avalanche power dissipation energy per unit area of this durable DMOS is 10 to 100 times higher than that of conventional VDMOSs. Although the breakdown voltage of this device is only 30V, no external protection device is required in automotive applications. Several fault phenomena which might occur in this device are also described. Two types of IPDs are proposed in this paper. One is a durable and low-cost high-side switch IPD, whose enhanced surge immunity of IC section from VDD line transient is verified by prototypes. Simplification of the fabrication process has also been achieved by lowering its breakdown voltage. The other is an extra-low on-resistance H-bridge IPD. Major on-resistance reduction of an output lateral type DMOS (LDMOS) is achieved because the cell-array structure is realized by applying 2-layer electrode technology to the power section. The on-resistance per unit area of this LDMOS is almost equal to that of VDMOSs in the same voltage class.
Masayoshi TAKEUCHI Masatoshi MIGITAKA
In order to develop silicon ICs operating up to above 450, Integrated Injection Logic (IIL) was chosen. A new structure for IIL was designed through experimental and theoretical studies of pn junctions, transistors, and IIL at high temperatures. A 5-µm design rule was used. The new IIL was fabricated by a specially developed combined process of ion implantation and low temperature epitaxy. The IIL was fully operational from room temperature to 454, and the output amplitude of a nine-stage ring oscillator was about 30 mV at 454. The minimum delay time of the IIL was 22 nsec at 454. The minimum power-delay product was 11 pJ and was one-third of that for IILs fabricated by 10-µm rule at 50.
For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.
Hidetoshi MATSUMOTO Yasunari UMEMOTO Yoshihisa OHISHI Mitsuharu TAKAHAMA Kenji HIRUMA Hiroto ODA Masaru MIYAZAKI Yoshinori IMAMURA
We have developed a new HIGFET structure achieving an extremely high K-value of 13.3 S/Vcm with a gate length of 0.15 µm. Self-aligned ion implantation is excluded to suppress a short-channel effect. An i-GaAs cap layer and an n+-GaAs contact layer are employed to reduce source resistance. The threshold voltage shift is as small as 50 mV when the gate length is reduced from 1.5 µm to 0.15 µm. Source resistance is estimated to be 53 mΩcm. We have also developed a new fabrication process that can achieve a shorter gate length than the minimum size of lithography. This process utilizes an SiO2 sidewall formed on the n+-GaAs contact layer to reduce the gate length. A gate length of 0.15 µm can be achieved using 0.35 µm lithography.
Reactive gases such air pollution agents as H2S or SO2 usually corrode the electrical contact surfaces. Since corrosion products formed on the surface increase contact resistance, they harmfully degrades contact reliability. To prevent the corrosion of the surface, oil coating on it may be effective. The oil film acts basically as a barrier for reaction between the corrosive gas and the surface. For thin film coating, the corrosion inhibition can not be expected. However, effect of film thickness on the corrosion property has not been clarified. In the present study, in order to clarify the corrosion inhibition of the oil coating for the contacts, the stearic acid coating on Ag (silver) contact surface was studied from view-point of the relationship between the thickness of the coating film and the contact resistance. As results, the effect of the stearic acid coating on corrosion inhibition in the atmosphere contained with H2S 3 ppm was found. However, the corrosion of the surface coated with thin stearic acid film occurred at microscopically scattered thin patiches in the specific pattern of the film. Existing of the optimum thickness of the stearic acid coating which gives both minimum contact resistance and effective corrosion inhibition was found. In the intermediate film thickness, this optimum thickness was induced by the increased contact resistance due to corrosion of the thin film region and insulation property of the stearic acid in the thick film region. Moreovr,it was found that this optimum thickness was affected by corrosion time. At the early stage of corrosion, the optimum thickness was about 200 . However, the corrosion time becomes longer as 700 min, this optimum thickness changed to thick as 1000 . With this increase in the thickness, the contact resistance in the optimum thickness rised to high level. Furthermore, the contact resistance in the optimum thickness decreased with increase in the contact load. However, dependence of the contact load on the optimum thickness was not recognized under a certain corrosion time.
Cosy MUTO Noriyoshi KAMBAYASHI
Complex filters are used to synthesize real filters in digital signal processing, but few in analog one. In this paper, we propose a leapfrog synthesis of complex analog filters. By shifting frequency response of an LCR network along the ω-axis, we have a complex filter with imaginary resistances, which is called an "LCRRi filter." The complex resonator is then used to simulate series- or parallel-arms of the LCRRi filter. We analyze nonideal properties of the complex resonator due to finite gain-bandwidth product of operational amplifiers and propose a compensation method to put a pole on correct location. Experimental results show good performance of the proposed method.