When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.

This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

Abnormal I_DDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.

In this paper, we analyze behaviors of bridging faults in CMOS synchronous sequential circuits based on transient analysis. From analysis results, we expose dynamic and analog behaviors of the circuit caused by the bridging faults, which are oscillation, asynchronous sequential behavior, IDDT failure and IDDQ failure as well as logic error. In order to detect this kind of fault, we show that not only IDDQ testing but also IDDT testing and logic testing which guarantees correct state transitions are required.

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearlized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies.

As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (Multi-Duty SCAN) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.

The partially rotational scan (PRS) technique greatly reduces the amount of data needed for n-detection testing. It also enables at-speed testing using low-speed testers. We designed tester intellectual properties (tester IP) with PRS for Viper and COMET II processors. When PRS was applied to a Viper processor, we obtained test data that provided the same fault coverage as with a set of automatic test pattern generation (ATPG) test vectors, although the amount of test data was 16% that of the ATPG. When the PRS technique was applied to a COMET II processor with full-scan design, we obtained test data that provided the same fault coverage as with a set of ATPG test vectors, although the amount of test data was 10% that of the ATPG. We also estimated hardware overhead and test time.

In this paper, we show a method to locate a single stuck-at fault of a random access memory (RAM). From the fail-bitmaps of the RAM, we obtain their Walsh spectrum. For a single stuck-at fault, we show that the fault can be identified and located by using only the 0-th and 1-st coefficients of the spectrum. We also show a circuit to compute these coefficients. The computation time is O(2ⁿ), where n is the number of bits in the address of the RAM. The computation time is much shorter than one that uses a logic minimization method.

Most of system-on-chips (SOCs) have many memory cores. Diagnosis is often used to improve the yield of memories. Memory cores usually represent a significant portion of the chip area and dominate the yield of the chip. Memory diagnosis thus is one of key techniques for improving the yield and quality of SOCs. Content addressable memories (CAMs) are important components in many SOCs. In this paper we propose a three-phase diagnosis procedure for binary CAMs (BCAMs). The user can distinguish different types of BCAM-specific comparison and RAM faults and locate the faulty cells with the procedure. A March-like fault identification algorithm is also proposed. The algorithm can distinguish different types of faults--including typical RAM faults and BCAM-specific comparison faults. The algorithm requires 15N Read/Write operations and 2(N + B) Compare operations for an N B-bit BCAM. Analysis results show that the algorithm has 100% diagnostic resolution for the target faults.

This paper proposes an SoC test architecture generation framework. It contains a database, which stores the test cost information of several DFTs for every core, and a DFT selection part which performs DFT selection for minimizing the test application time using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm that solves this problem is proposed. Experimental results show that bottlenecks in test application time when using a single DFT method for all cores in an SoC is reduced by performing DFT selection from two types of DFTs. As a result, the whole test application time is drastically shortened.

In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.

This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.

Coefficient-based test (CBT) is introduced for detecting parametric faults in analog circuits. The method uses pseudo Monte-Carlo simulation and system identification tools to determine whether a given circuit under test (CUT) is faulty.

A reversible cellular automaton (RCA) is a computing model having a property analogous to physical reversibility. We investigate the problem of finding simple RCAs in which any circuit composed of rotary elements (REs) can be embedded. Since an RE is known to be a universal reversible logic element, such RCAs are also universal in this respect. In this paper, after giving a survey of known results on RE and its implementation in RCAs, we propose a new RCA model in which REs and some signal routing elements can be embedded. The new model has a simpler local transition function (in the sense it is described by fewer rules) than the previous one, though the number of states is the same. In addition, the patterns realizing an RE and signal routing elements are smaller than those of the previous model.

This paper studies the propagation and crossing of signals in cellular automata whose cells are updated at random times. The signals considered consist of a core part, surrounded by an insulating sheath that is missing at the side of the core that corresponds to the direction into which the signal moves. We study two types of signals: (1) signals by which the sheath at the left and right sides of the core advance first in a propagation step, followed by the core, and (2) signals by which the core advances first, followed by the sheath at its left and right sides. These types naturally arise in, respectively, Moore neighborhood cellular automata with semi-totalistic rules and von Neumann neighborhood cellular automata with symmetric transition rules. The type of a signal has a profound impact on the way signals cross each other, as we show by the construction of one signal of each type. The results we obtained should be of assistance in constructing asynchronous circuits on asynchronous cellular automata.

This paper presents a Multi Agent Systems (MAS) approach to crowd modelling, based on the Situated Cellular Agents (SCA) model. This is a special class of Multilayered Multi Agent Situated System (MMASS), providing an explicit representation of spatial structures and different means of agent interaction. Heterogenous agents may be obtained through the definition of different agent types, specifying different behaviors and perceptive capabilities. The model is rooted on some basic principles of Cellular Automata (e.g. the definition of adjacency geometries), but also takes into account the autonomy of modelled entities, with their own internal architecture. A formal definition of the SCA model will be given, with a description of how it can be applied to forward and backward approaches to simulation. Particular attention will be paid to the crowd and pedestrian modelling, and two applications to simulation to crowding will be described.

In this paper, we investigate how to initialise cellular automata implemented in the hyperbolic plane. We generalise a technique which was indicated in to the case of any rectangular regular grid of the hyperbolic plane. This allows us to construct the initial configuration of any cellular automaton belonging to a rather large class of problems.

The capabilities of reliable computations in one-dimensional cellular automata are investigated by means of the Early Bird Problem. The problem is typical for situations in massively parallel systems where a global behavior must be achieved by only local interactions between the single elements. The cells that cause the misoperations are assumed to behave as follows. They run a self-diagnosis before the actual computation once. The result is stored locally such that the working state of a cell becomes visible to its neighbors. A non-working (defective) cell cannot modify information but is able to transmit it unchanged with unit speed. We present an O(n log (n) log (n))-time fault-tolerant solution of the Early Bird Problem.

A number-conserving cellular automaton (NCCA) is a cellular automaton (CA) such that all states of cells are represented by integers and the sum of the cell states is conserved throughout its computing process. It can be thought of as a kind of modelization of the physical conservation law of mass or energy. It is known that the local function of a two-dimensional 45-degree reflection-symmetric von Neumann neighbor NCCA can be represented by linear combinations of a binary function. In spite of the number-conserving constraints, it is possible to design an NCCA with complex rules by employing this representation. In this paper, we study the case in which the binary function depends only on the difference of two cell states, i.e., the case in which the function can be regarded as a unary one and its circuit for applying rules to a cell only need adders and a single value table look up module. Even under this constraint, it is possible to construct a logically universal NCCA.

This paper investigates relationships among deterministic, nondeterministic, and alternating complexity classes defined in the hyperbolic space. We show that (i) every t(n)-time nondeterministic cellular automaton in the hyperbolic space (hyperbolic CA) can be simulated by an O(t⁴(n))-space deterministic hyperbolic CA, and (ii) every t(n)-space nondeterministic hyperbolic CA can be simulated by an O(t²(n))-time deterministic hyperbolic CA. We also show that n^r+-time (non)deterministic hyperbolic CAs are strictly more powerful than n^r-time (non)deterministic hyperbolic CAs for any rational constants r 1 and > 0. From the above simulation results and a known separation result, we obtain the following relationships of hyperbolic complexity classes: P_h= NP_h = PSPACE_h EXPTIME_h= NEXPTIME_h = EXPSPACE_h , where C_h is the hyperbolic counterpart of a Euclidean complexity class C. Furthermore, we show that (i) NP_h AP_h unless PSPACE = NEXPTIME, and (ii) AP_h EXPTIME _h.

This paper investigates prefix computations on Iterative Arrays (IAs) with sequential input/output mode. We show that, for any language L accepted by a linear-time IA, there is an IA which, given an infinite string a₁a₂ a_i, generates the values of χ_L(a₁),χ_L(a₁a₂),,χ_L(a₁a₂ a_i), at steps 4,16,,4i²,, respectively. Here, χ_L:Σ^*{0,1} is the characteristic function of the language L Σ^*, defined as χ_L(w) = 1 iff w L. We also construct 2i³-time and i⁴-time prefix algorithms for languages accepted by quadratic-time and cubic-time IAs, respectively.

Automata based image compression methods exploit similarities in the images to reduce the amount of memory to the essential. Our cellular automata methods are motivated due to the fact that they may be used to create images on liquid crystal displays when we add some computational functionality to the displays. For this purpose we consider image generation methods in cellular automata with some reasonable restrictions and get a representation where the color values of the images can be derived directly from the single cell states. We are interested in the capabilities of such devices and provide some benefits of this representation in image compression, even in higher dimensions.

The descriptional complexity of iterative arrays (IAs) is studied. Iterative arrays are a parallel computational model with a sequential processing of the input. It is shown that IAs when compared to deterministic finite automata or pushdown automata may provide savings in size which are not bounded by any recursive function, so-called non-recursive trade-offs. Additional non-recursive trade-offs are proven to exist between IAs working in linear time and IAs working in real time. Furthermore, the descriptional complexity of IAs is compared with cellular automata (CAs) and non-recursive trade-offs are proven between two restricted classes. Finally, it is shown that many decidability questions for IAs are undecidable and not semidecidable.

The floor field model, which is a cellular automaton model for studying evacuation dynamics, is investigated and extended. A method for calculating the static floor field, which describes the shortest distance to an exit door, in an arbitrary geometry of rooms is presented. The wall potential and contraction effect at a wide exit are also proposed in order to obtain realistic behavior near corners and bottlenecks. These extensions are important for evacuation simulations, especially in the case of panics.

In this paper we study a classical firing squad synchronization problem on a model of fault-tolerant cellular automata that have possibly some defective cells. Several fault-tolerant time-efficient synchronization algorithms are developed based on a simple freezing-thawing technique. It is shown that, under some constraints on the distribution of defective cells, any cellular array of length n with p defective cell segments can be synchronized in 2n - 2 + p steps.

Normally, flow field is described with governing equations, such as the Navier-Stokes equations. However, for complex flow including multiphase and reactive flow such as combustion, this approach may not be suitable. As an alternative approach, Lattice Gas Automata (LGA) has been used to simulate fluid with mesoscopic particles by assuming that space and time are discrete, and the physical quantities take only a finite set of values. In this study, the model for combustion simulation is proposed, with the reaction probability depending on the local temperature to simplify the chemical reaction. Here, counter-flow twin flames are simulated. In order to validate this approach, some results of non-reactive flow are presented, compared with those by solving Navier-Stokes equations.

This study addresses the problem of computing the reliability of stochastic binary systems. This computational problem is known as the problem of the union of a set of events, where each event is expressed as the product of a set of Boolean variables. It is assumed that each Boolean variable may take on either of two states: operative or failed. Computing the reliability of stochastic binary systems is known to be #P-complete. The computation remains #P-complete, even when all events have a cardinality two, and both elements of each event are selected from two disjoint sets. This study proposes a linear time algorithm to compute the reliability of stochastic binary systems when the events satisfy specific requirements.

Advances in ILP techniques enable strict consistency models to relax memory order through speculative execution of memory operations. However, ordering constraints still hinder the performance because speculatively executed operations cannot be committed out of program order for the possibility of mis-speculation. In this paper, we propose a new technique which allows memory operations to be non-speculatively committed out of order without violating consistency constraints. Consistency constraints are guaranteed through delaying the coherence requests. The proposed technique also improves the performance of spin lock primitives such as TTS lock or MCS lock. Through delaying early acquire requests, the lock transfer time can be improved when there is high contention for a lock.

Mining generalized frequent patterns of generalized association rules is an important process in knowledge discovery system. In this paper, we propose a new approach for efficiently mining all frequent patterns using a novel set enumeration algorithm with two types of constraints on two generalized itemset relationships, called subset-superset and ancestor-descendant constraints. We also show a method to mine a smaller set of generalized closed frequent itemsets instead of mining a large set of conventional generalized frequent itemsets. To this end, we develop two algorithms called SET and cSET for mining generalized frequent itemsets and generalized closed frequent itemsets, respectively. By a number of experiments, the proposed algorithms outperform the previous well-known algorithms in both computational time and memory utilization. Furthermore, the experiments with real datasets indicate that mining generalized closed frequent itemsets gains more merit on computational costs since the number of generalized closed frequent itemsets is much more smaller than the number of generalized frequent itemsets.

Among several methods of storing XML documents, a straightforward yet efficient method is to store a string representation of the XML document. An XML node is usually represented by a region coordinate, which is a pair of integers expressing the start and end positions of the substring corresponding to the node. This approach, however, has the drawback that a change of a node's region coordinate causes change of the region coordinates of many other elements. This recomputation normally degrades the performance of XML applications, especially when content is updated frequently. In this paper, we propose the Relative Region Coordinate (RRC) technique to effectively reduce the cost of recomputation. The main idea is to express the coordinate of an XML element in the region of its parent element. We present a method to integrate the RRC information into XML systems and provide experimental results that demonstrate the effectiveness of the RRC in the content update.

The number and location of the inventory centers play an important role in the material distribution process since residents and inventory centers may be in dispersed regions. In this paper, we view the problem of finding the better locations for the inventory centers as an optimization problem, and propose a nested genetic algorithm (NGA) approach to design an optimal material distribution system. We demonstrate the feasibility of the proposed approach by numerical experiments.

Image segmentation is an essential technique of image analysis. In spite of the issues in contour initialization and boundary concavities, active contour models (snakes) are popular and successful methods for segmentation. In this paper, we present a new active contour model, Gaussian Gradient Force snake (GGF snake), for segmentation of an endoscopic image. The GGF snake is less sensitive to contour initialization and it ensures a high accuracy, large capture range, and fast CPU time for computing an external force. It was observed that the GGF snake produced more reasonable results in various image types : simple synthetic images, commercial digital camera images, and endoscopic images, than previous snakes did.