Power efficiency and real-time processing capability are two major issues in today's mobile video applications. We proposed a novel Motion Estimation (ME) engine for power-efficient real-time MPEG-4 video coding based on our previously proposed content-based ME algorithm [8],[13]. By adopting Full Search (FS) and Three Step Search (TSS) alternatively according to the nature of video contents, this algorithm keeps the visual quality very close to that of FS with only 3% of its computational power. We designed a flexible Block Matching (BM) Unit with 16-PE SIMD data path so that the adaptive ME can be performed at a much lower clock frequency and hardware cost as compared with previous FS based work. To reduce the energy cost caused by excessive external memory access, on-chip SRAM is also utilized and optimized for parallel processing in the BM Unit. The ME engine is fabricated with TSMC 0.18 µm technology. When processing QCIF (15 fps) video, the estimated power is 2.88 mW@4.16 MHz (supply voltage: 1.62 V). It is believed to be a favorable contribution to the video encoder LSI design for mobile applications.

An improved algorithm for fast motion estimation based on the block matching algorithm (BMA) is presented for use in a block-based video coding system. To achieve enhanced motion estimation performance, we propose an adaptive search pattern length for each iteration for the current macro block (MB). In addition, search points that must be checked are determined by means of directional information from the error surface, thus reducing intermediate searches. The proposed algorithm is tested with several sequences and excellent performance is verified.

To drastically reduce the dynamic power (PAT) and the leakage power (PST) of the CMOS MPEG4/H.264 motion estimation (ME) circuits, several power reduction techniques were developed. They were circuit architectures, which were able to reduce the supply voltages (VDD) and numbers of logic gates of not only the whole circuit but the critical path, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.18-µm CMOS ME circuit has been fabricated by adopting those techniques. At a clock frequency of 160 MHz and VDD of 1.25 V, PAT decreased to 75.9 µW, which was 5.35% that of a conventional ME circuit. PST also decreased to 0.82 nW, which was 3.93% that of the conventional ME circuit.

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

This paper describes an objective measurement method designed to assess the perceived quality for digital videos. The proposed approach can be used either in the context of a reduced reference quality assessment or in the more challenging situation where no reference is available. In that way, it can be deployed in a QoS monitoring strategy in order to control the end-user perceived quality. The originality of the approach relies on the very limited computation resources which are involved, such a system could be integrated quite easily in a real time application. It uses a convolutional neural network (CNN) that allows a continuous time scoring of the video. Experiments conducted on different MPEG-2 videos, with bit rates ranging from 2 to 6 Mbits/s, show the effectiveness of the proposed approach. More specifically, a linear correlation criterion, between objective and subjective scoring, ranging from 0.90 up to 0.95 has been obtained on a set of typical TV videos in the case of a reduced reference assessment. Without any reference to the original video, the correlation criteria remains quite satisfying since it still lies between 0.85 and 0.90, which is quite high with respect to the difficulty of the task, and equivalent and more in some cases than the traditional PSNR, which is a full reference measurement.

This paper presents a correlation-based watermarking method for video using the similarity of adjacent frames. In general, the adjacent frames of a video sequence is very similar. In the proposed scheme, we use an adjoining frame in detection process instead of an original image in the watermarking scheme of Cox et al. So the proposed method does not need an original video sequence in detection process. When a watermarked video sequence is attacked by overwriting copy or frame dropping, the pair of the frames that is not adjoining in an original video sequence is used in detection process. However, since a watermark is embedded in a part of each frame and embedding positions are different for each frame in the proposed method, we can detect the watermark even from an overwriting-copied video sequence and a frame-dropped video sequence. Experimental results show that the proposed method is robust against overwriting copy and frame dropping. Moreover, it is shown from experimental results that the method has robustness to low bitrate MPEG compression and StirMark attack.

With the increase of commercial multimedia applications using digital video, the security of video data becomes more and more important. Although several techniques have been proposed in order to protect these video data, they provide limited security or introduce significant overhead. This paper proposes a video security scheme for MPEG video compression standard, which includes two methods: DCEA (DC Coefficient Encryption Algorithm) and "Event Shuffle." DCEA is aim to encrypt group of codewords of DC coefficients. The feature of this method is the usage of data permutation to scatter the ciphertexts of additional codes in DC codewords. These additional codes are encrypted by block cipher previously. With the combination of these algorithms, the method provides enough security for important DC component of MPEG video data. "Event Shuffle" is aim to encrypt the AC coefficients. The prominent feature of this method is a shuffling of AC events generated after DCT transformation and quantization stages. Experimental results show that these methods introduce no bit overhead to MPEG bit stream while achieving low processing overhead to MPEG codec.

This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.

In this paper, we present a novel iterative MPEG super-resolution method based on an embedded constraint version of Adaptive projected subgradient method [Yamada & Ogura 2003]. We propose an efficient operator that approximates convex projection onto a set characterizing framewise quantization, whereas a conventional method can only handle a convex projection defined for each DCT coefficient of a frame. By using the operator, the proposed method generates a sequence that efficiently approaches to a solution of super-resolution problem defined in terms of quantization error of MPEG compression.

This paper describes a distributed video transcoding system that can simultaneously transcode an MPEG-2 video file into various video coding formats with different rates. The transcoder divides the MPEG-2 file into small segments along the time axis and transcodes them in parallel. Efficient video segment handling methods are proposed that minimize the inter-processor communication overhead and eliminate temporal discontinuities from the re-encoded video. We investigate how segment transcoding should be distributed to obtain the shortest total transcoding time. Experimental results show that implementing distributed transcoding on 10 PCs can decrease the total transcoding time by a factor of about 7 for single transcoding and by a factor of 9.5 for simultaneous three kinds of transcoding rates.

The latest video coding standard, H.264/AVC, adopts 44 approximate transform instead of 88 discrete cosine transform (DCT) to avoid the inverse transform mismatch problem. However, that is only one of the factors that make it difficult to transcode pre-coded video contents with the previous standards to H.264/AVC in the common domain without causing cascaded pixel-domain transcoding. In this paper, to support the existent DCT-domain transcoding schemes and to reduce computational complexity, we propose an efficient algorithm that converts the quantized 88 DCT block into four newly quantized 44 transformed blocks. The experimental results show that the proposed scheme reduces computational complexity by 5-11% and improves video quality by 0.1-0.5 dB compared with the cascaded pixel-domain transcoding scheme that exploits inverse quantization (IQ), inverse DCT (IDCT), DCT, and re-quantization (re-Q).

Recent microprocessors have included SIMD (single instruction multiple data) extensions into their instruction set architecture to improve the performance of multimedia applications. SIMD instructions speed up the execution of programs but pose lots of challenges to software developers. An efficient matrix-based splitter (or merger), which can split an N N 2-D DCT block into four N/2 N/2 or two N N/2 (or N/2 N) 2-D DCT blocks (or merger small size blocks into a large size one), specialized for SIMD architectures is presented in this paper. The programming-level complexity of the proposed methods is lower than that of the direct approach. Furthermore, even without using SIMD instructions, the algorithmic-level complexity of the proposed DCT splitter/merger is still lower than that of the direct one and is the same as that of the most efficient approach existed in the literature. When N = 8, our method can be applied to act as a transcoder between the latest video coding standards AVC/H.264 and the older ones, such as MPEG-1, MPEG-2 and MPEG-4 part 2. We also provide the image quality tests to show the performance of the proposed 2-D DCT splitter and merger.

This paper presents a semi-automatic algorithm for video object segmentation. Our algorithm assumes the use of multiple key video frames in which a semantic object of interest is defined in advance with human assistance. For video frames between every two key frames, the specified video object is tracked and segmented automatically using Learning Vector Quantization (LVQ). Each pixel of a video frame is represented by a 5-dimensional feature vector integrating spatial and color information. We introduce a parameter K to adjust the balance of spatial and color information. Experimental results demonstrate that the algorithm can segment the video object consistently with less than 2% average error when the object is moving at a moderate speed.

This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.

In this paper, we present an MPEG-4 decoding scheme based on reversible variable length code. The scheme is purely decoder based and compliance with the standard is fully maintained. Moreover, the data recovery scheme suggested in MPEG-4 can still be used as the default scheme. Simulation results show that the proposed scheme achieves better data recovery, both in terms of PSNR and perceptual quality, from error propagation region of a corrupted video packet, as compared to existing MPEG-4 scheme.

In this paper, a new error concealment algorithm for MPEG-4 object-based video is presented. The algorithm consists of a feature matching step to identify temporally corresponding features between video frames and an affine parameter estimation step to find the motion of the feature points. In the feature matching step, an efficient cross-radial search (CRS) method is developed to find the best matching points. In the affine parameter estimation step, a non-iterative least squares estimation algorithm is developed to estimate the affine parameters. An attractive feature of the algorithm is that the shape data and texture data are handled by the same method. Unlike previous methods, this unified approach works for the case where the video object undergoes a drastic movement, such as a sharp turn. Experimental results show that the proposed algorithm performs much better than previous approaches by about 0.3-2.8 dB for shape data and 1.6-5.0 dB for texture data.

This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.

This paper introduces the water ring scan method especially designed for the scalable video coding schemes such as fine granularity scalabilities (FGS) on the basis of MPEG-4 part-2 and the H.264. The proposed scanning method can improve the subjective quality of the decoded video by most-preferentially encoding, transmitting and decoding the image information of the region of interest. From the various simulation results of FGS coding schemes with MPEG-4 part 2 and H.264, the proposed scanning method can improve the subjective picture quality about 0.5 dB 3.5 dB better than the widely used raster scan order, especially on the region of interest, without significant loss of the quality in the left-over region.

We consider the edge-linking approach for accurate locating of moving object boundaries in video segmentation. We review the existing methods and propose a scheme designed for efficiency and better accuracy. The scheme first obtains a very rough outline of an object by a suitable means, e.g., change detection. It then forms a relatively compact image region that properly contains the object, through a procedure termed "mask sketch." Finally, the outermost edges in the region are found and linked via a shortest-path algorithm. Experiments show that the scheme yields good performance.

In this paper, we propose an MPEG-2 TS encryption and decryption scheme which can support MPEG-2 TS streaming, and a key management scheme which can provide secure delivery of the key used to encrypt MPEG-2 TS from the package server to DRM clients in a secure manner. The key management scheme protects the key not only from purchasers but also among the other principals who manage the distribution servers and license servers. The proposed scheme can protect from attacks over a network since a pre-encrypted MPEG-2 TS is sent by a streaming server and only DRM clients can decrypt the streamed MPEG-2 TS. An MPEG-2 TS streaming server can send the encrypted stream without modifying it and degrading its performance because MPEG-2 TS is encrypted but compliant to the MPEG-2 TS format. The processing time to decrypt a streamed MPEG-2 TS in client systems is minimized to guarantee the quality of streaming.