This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.

This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.

Negative feedback technique employing high DC gain operational amplifier (op-amp) is one of the most important techniques in analog circuit design. However, high DC gain op-amp is difficult to realize in scaled technology due to a decrease of intrinsic gain. In this paper, high DC gain op-amp using common-gate topology with high power efficiency is proposed. To achieve high DC gain, large output impedance is required but input transistors' drain conductance decreases output impedance of conventional topology such as folded cascode topology with complementary input. This is because bias current of the output side transistors is not separated from the bias current of the input transistors. On the other hand, proposed circuit can suppress a degradation of output impedance by inserting common-gate topology between input and output side. This architecture separates bias current of the input transistors from that of the output side, and hence the effect of the drain conductance of input transistors is reduced. As the result, proposed circuit can increase DC gain about 10,dB compared with the folded cascode topology with complementary input in 65,nm CMOS process. Moreover, power consumption can be reduced because input NMOS and PMOS share bias current. According to the simulation results, for the same power consumption, in the proposed circuit gain-bandwidth product (GBW) is improved by approximately 30% and noise is also reduced in comparison to the conventional topology.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.