This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.

LiDAR is a distance sensor that plays a key role in the realization of advanced driver assistance systems (ADAS). In this paper, we present a tutorial and review of automotive direct time of flight (dToF) LiDAR from the aspect of circuit systems. We discuss the breakthrough in ADAS LiDARs through comparison with the first-generation LiDAR systems, which were conventionally high-cost and had an immature performance. We define current high-performance and low-cost LiDARs as next-generation LiDAR systems, which have significantly improved the cost and performance by integrating the photodetector, the readout circuit, and the signal processing unit into a single SoC. This paper targets reader who is new to ADAS LiDARs and will cover the basic principles of LiDAR, also comparing with range methods other than dToF. In addition, we discuss the development of this area through the latest research examples such as the 2-chip approach, 2D SPAD array, and 3D integrated LiDARs.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

This paper proposes a triangular active charge injection method to reduce resonant power supply noise by injecting the adequate amount of charge into the supply line of the LSI in response to the current consumption of the core circuit. The proposed circuit is composed of three key components, a voltage drop detector, an injection controller circuit and a canceling capacitor circuit. In addition to the theoretical analysis of the proposed method, the measurement results indicate that our proposed method with active capacitor can realize about 14% noise reduction compared with the original noise amplitude. The proposed circuit consumes 25.2 mW in steady state and occupies 0.182 mm2.

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-µm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64dB is achievable at an input signal frequency of 10kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

We present a time-to-digital converter (TDC) achieving sub-picosecond resolution and high precision for all-digital phase-locked-loops (ADPLLs). The basic idea is using a charge pump to translate time interval into charge, and a successive-approximation-register-analog-to-digital converter (SAR-ADC) to quantize the charge. With this less complex configuration, high resolution, high precision, low power, and small area can be achieved all together. We analyzed the noise contribution from the charge pump and describe detailed design and implementation for sizing the capacitor and transistors, with the awareness of noise and linearity. The analysis demonstrates the proposed TDC capable of sub-picosecond resolution and high precision. Two prototype chips were fabricated in 65nm CMOS with 0.06mm2, and 0.018mm2 core areas, respectively. The achieved resolutions are 0.84ps and 0.80ps, in 8-bit and 10-bit range, respectively. The measured single-shot-precisions range from 0.22 to 0.6ps, and from 0.66 to 1.04ps, respectively, showing consistent trends with the analysis. Compared with state-of-the-arts, best performance balance has been achieved.

We have been developing a superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconductive strip ion detector (SSID) and a single-flux-quantum (SFQ) multi-stop time-to-digital converter (TDC). The SFQ multi-stop TDC can measure the time intervals between multiple input signals and directly convert them into binary data. In this study, we designed and implemented 24-bit SFQ multi-stop TDCs with a 3×24-bit FIFO buffer using the AIST Nb standard process (STP2), whose time resolution and dynamic range are 100ps and 1.6ms, respectively. The timing jitter of the TDC was investigated by comparing two types of TDCs: one uses an on-chip SFQ clock generator (CG) and the other uses a microwave oscillator at room temperature. We confirmed the correct operation of both TDCs and evaluated their timing jitter. The experimentally-obtained timing jitter is about 40ns and 700ps for the TDCs with and without the on-chip SFQ CG, respectively, for the measured time interval of 50µs, which linearly increases with increase of the measured time interval.

This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.

This paper proposes a coarse-fine Time-to-Digital Converter (TDC), based on a Ring-Tapped Delay Line (RTDL). The TDC achieves the picosecond's level timing resolution and microsecond's level dynamic range at low cost. The TDC is composed of two coarse time measurement blocks, a time residue generator, and a fine time measurement block. In the coarse blocks, RTDL is constructed by redesigning the conventional Tapped Delay Line (TDL) in a ring structure. A 12-bit counter is employed in one of the two coarse blocks to count the cycle times of the signal traveling in the RTDL. In this way, the input range is increased up to 20.3µs without use of an external reference clock. Besides, the setup time of soft-edged D-flip-flops (SDFFs) adopted in RTDL is set to zero. The adjustable time residue generator picks up the time residue of the coarse block and propagates the residue to the fine block. In the fine block, we use a Vernier Ring Oscillator (VRO) with MOS capacitors to achieve a scalable timing resolution of 11.8ps (1 LSB). Experimental results show that the measured characteristic curve has high-level linearity; the measured DNL and INL are within ± 0.6 LSB and ± 1.5 LSB, respectively. When stimulated by constant interval input, the standard deviation of the system is below 0.35 LSB. The dead time of the proposed TDC is less than 650ps. When operating at 5 MSPS at 3.3V power supply, the power consumption of the chip is 21.5mW. Owing to the use of RTDL and VRO structures, the chip core area is only 0.35mm × 0.28mm in a 0.35µm CMOS process.

This paper presents an M-channel (M=2n (n ∈ N)) integer discrete cosine transforms (IntDCTs) based on fast Hartley transform (FHT) for lossy-to-lossless image coding which has image quality scalability from lossy data to lossless data. Many IntDCTs with lifting structures have already been presented to achieve lossy-to-lossless image coding. Recently, an IntDCT based on direct-lifting of DCT/IDCT, which means direct use of DCT and inverse DCT (IDCT) to lifting blocks, has been proposed. Although the IntDCT shows more efficient coding performance than any conventional IntDCT, it entails many computational costs due to an extra information that is a key point to realize its direct-lifting structure. On the other hand, the almost conventional IntDCTs without an extra information cannot be easily expanded to a larger size than the standard size M=8, or the conventional IntDCT should be improved for efficient coding performance even if it realizes an arbitrary size. The proposed IntDCT does not need any extra information, can be applied to size M=2n for arbitrary n, and shows better coding performance than the conventional IntDCTs without any extra information by applying the direct-lifting to the pre- and post-processing block of DCT. Moreover, the proposed IntDCT is implemented with a half of the computational cost of the IntDCT based on direct-lifting of DCT/IDCT even though it shows the best coding performance.

We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 µm2 and 281 µW.

This paper presents a second-order ΔΣ analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 µW. Its area is 608 µm2.

This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.

In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm2. And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 µm and L = 0.18 µm in a 1616 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 to 75. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.

This paper presents an integer discrete cosine transform (IntDCT) with only dyadic values such as k/2n (k, n∈ in N). Although some conventional IntDCTs have been proposed, they are not suitable for lossless-to-lossy image coding in low-bit-word-length (coefficients) due to the degradation of the frequency decomposition performance in the system. First, the proposed M-channel lossless Walsh-Hadamard transform (LWHT) can be constructed by only (log2M)-bit-word-length and has structural regularity. Then, our 8-channel IntDCT via LWHT keeps good coding performance even if low-bit-word-length is used because LWHT, which is main part of IntDCT, can be implemented by only 3-bit-word-length. Finally, the validity of our method is proved by showing the results of lossless-to-lossy image coding in low-bit-word-length.