This letter presents a novel method to design a power distribution network with highly accurate impedance characteristic. Based on the PBEC (path-based equivalent circuit) model and the network synthesis, the proposed design method exploits simple arithmetic expressions to calculate the electrical parameters of a power distribution network. It directly calculates and determines the size of on-chip decoupling capacitors, the size and location of off-chip decoupling capacitors, and the effective inductances of the package power bus. To evaluate the accuracy of the proposed method, it was applied to a test board with size of 12.5 cm 12.5 cm and with plane-to-plane distance of 200 µm. The proposed method successfully designed a power distribution network keeping its impedance characteristic under 1 Ω with frequency range of 100 kHz-1 GHz. The proposed design method requires negligible computation when compared with conventional PEEC (partial elements equivalent circuit) model-based design approaches, but the simulation results of both methods are almost identical. Consequently, the proposed method enables simple, fast and accurate design of power-distribution networks, which gives economic and practical solutions for commercial tools.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

This letter considers relationship between cyclic digital-to-analog converters (DACs) and iterated function systems (IFSs). We introduce the cyclic DACs as inverse systems of analog-to-digital converters in terms of one-dimensional maps. We then compare the DACs with a typical example of existing applications of IFSs: chaos game representation for analysis of DNA structures. We also present a simple test circuit of a DAC for Gray decoding based on switched capacitors and confirm the basic operation experimentally.

Dynamic non-linearities are of more importance in highly-linear high-speed applications such as software radios. In this paper, a fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-to-digital converters (ADCs) in the presence of circuit non-idealities is presented. These imperfections include the capacitor mismatches and the non-idealities in the operational amplifiers (op-amps). The most two important ADC dynamic non-linearity parameters, the spurious-free dynamic range (SFDR) and the signal-to-noise-and-distortion ratio (SNDR) are quantified here and closed-form formulas are presented. These formulas are useful for design automation as well as hand calculations of highly-linear pipeline ADCs. Behavioral simulations are presented to show the accuracy of the proposed equations.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

A switched capacitor DC-DC voltage converter that has an arbitrary conversion ratio of rational number is presented. A given voltage conversion ratio is systematically expanded to construct a switched capacitor circuit that operates with a two-phase switching clock. The conversion ratio is completely free from capacitance values and ratios under the assumption that there is no charge transfer between the two switching phases. This means that the converter cannot supply any power to the load. This restricts the application of the converters to a very limited area such as a voltage reference generator that only provides a reference voltage and no power to a circuit. The conditions for the convergence of the output voltage and the stray capacitor effects are discussed. The output voltage error and required switching frequency are also discussed when the converter is used as a DC voltage supply source that provides power to a load.

In this paper, a new full on-chip high efficiency DC-DC voltage up converter with no inductance element is presented with power efficiency more than 74%. A method in the charge pump is described to have a regulated 3.3 V from 1.5 V for output power 4 mW. For medium power class, 100-200 mW, a boost converter is designed with on-chip inductor for 1.5 V to 3.3 V conversion. A buck converter is also designed for 3.3 V to 1 V conversion with power efficiency 72%. Inductor property of bond-wire is employed in the on-chip inductors. Analysis of efficiency relations and simulation results are presented for 0.35 µm CMOS technology.

Delta-sigma modulators (DSMs) are commonly use in high-resolution analog-to-digital converters, and band-pass delta-sigma modulators have recently been used to convert IF signals into digital signals. In particular, a quadrature band-pass delta-sigma modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. The current paper proposes a second-order three-bit quadrature band-pass delta-sigma modulator that can achieve a lower power consumption and better performance with a similar die size to a conventional fourth-order quadrature band-pass delta-sigma modulator (QBPDSM). The proposed system is integrated using CMOS 0.35 µm, double-poly, four-metal technology. The system operates at 13 MHz and can digitize a 200 kHz bandwidth signal centered at 4.875 MHz with an SNR of 85 dB. The power consumption is 35 mW at 3.3 V and 38 mW at 5 V, and the die size is 21.9 mm2.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.

InGaP/GaAs HBT with novel ledge coupled capacitor (LCC) structure has been proposed and demonstrated for the first time. The LCC employs an extrinsic InGaP ledge layer as a capacitor parallel to the base resistor. This configuration enables feeding RF signals directly into the base without passing them through the base resistor. With the fabricated HBT, no increase of leakage current between emitter and base electrode was observed. The maximum oscillation frequency (fmax) of the HBT was improved by 10 GHz as compared with an HBT without the LCC.

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

The design, fabrication, and characterization of monolithic analog phase shifters based on barium-strontium-titanate (BST) coated sapphire substrates with continuously variable 180and 360phase-shift ranges are presented. The phase shifter using a single series resonated termination can provide 180phase shift with the chip area of 4 mm 4 mm. A double series resonated termination in a parallel connection can reach over 370phase shift with better than 6.8 dB-loss at 2.4 GHz. Also, an all-pass network phase shifter composed of only lumped LC elements was described here. This phase shifter demonstrated 160phase shift with an insertion loss of 3.1 dB 1 dB and return loss of better than 10 dB at 2.4 GHz. The total size of the phase shifter is only 2.4 mm 2.6 mm, which is the smallest reported BST phase shifter operating at S-band, to the best of the authors' knowledge.

We have thoroughly investigated the effect of on-chip decoupling capacitors on the simultaneous switching noise (SSN) and the radiated emission. Furthermore, we have successfully demonstrated an efficient design method for on-chip decoupling capacitors on an 8-bit microcontroller without increasing the die size, which results in more than 10 dB of suppressed radiated emission.

A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm 245µm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

Electroluminescence (EL) under alternating-current (ac) operation is first reported for n+-polysilicon/SiO2/p-Si MOS capacitors with 50 nm Si-implanted SiO2. Visible EL can be observed with the naked eye in the dark. The ac operation by pulse-wave distinctly enhances the EL intensity and its lifetime. The pulse frequency affects the EL spectrum and thus the EL color. A model of EL mechanism is proposed for the Si-implanted MOS EL device, which has a possibility of visible light emitting device.

As two simple relaxation oscillators are coupled by periodical and instantaneous switching, the system exhibits rich superstable synchronous phenomena. In order to analyze the phenomena, we derive a hybrid return map of real and binary variables; and give theoretical results for (1) superstability of the synchronous phenomena and (2) period of the synchronous phenomena as a function of the parameters. Using a simple test circuit, typical phenomena are verified in the laboratory.

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.