Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18 µm CMOS technology, and the simulation results show 86 dB of dynamic range with 4.5 µVrms of input-referred noise for an audio bandwidth of 20 kHz and a total harmonic distortion (THD) of 1% at 90 mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95 dB at 1 kHz. The proposed design dissipates 125 µA and can operate over a wide supply voltage range of 1.6 V to 3.3 V.

This letter proposes a mismatch insensitive switched-capacitor multiply-by-four (4X) amplifier using the voltage addition scheme. The proposed circuit provides 2-times faster speed and about half of silicon area when compared with the cascade of conventional 2X amplifiers. Monte-Carlo simulation results show about 15% gain accuracy improvement over the cascaded 2X- amplifiers.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 µm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

Capacitor mismatch is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. In this paper we describe the impact of leakage current on the technique. The leakage can come from, for example, thin gate oxide MOSFETs or high dielectric constant capacitors in advanced technologies. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. Criteria for accurate capacitor systematic and random mismatch characterization are developed, and practical methods of increasing measurement accuracy are discussed.

A fuzzy logic control battery equalizing controller (FLC-BEC) is adopted to control the cell voltage balancing process for a series connected Li-ion battery string. The proposed individual cell equalizer (ICE) is based on the bidirectional Cuk converter operated in the discontinuous capacitor voltage mode (DCVM) to reduce the switching loss and improve equalization efficiency. The ICE with the proposed FLC-BEC can reduce the equalizing time, maintain safe operations during the charge/discharge state and increase the battery string capacity.

This paper reviews techniques for digitally assisted pipeline ADCs. Errors of pipeline ADCs originated by capacitor mismatch, finite amplifier gain, incomplete settling and offset can be corrected in digital-domain foreground or background calibrations. In foreground calibrations, the errors are measured by reconfiguration of the building blocks of pipeline ADC or using an INL plot without reconfiguration. In background calibrations, the errors are measured with random signal and continuously corrected while simultaneously performing the normal A/D conversions. Techniques for measuring and correcting the errors at foreground and background are reviewed and a unified approach to the description of the principle of background calibration of gain errors is presented.

A cross-coupled charge pump with internal pumping capacitor, which is advantageous from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using NMOS and PMOS diodes connected to boosting nodes from VIN nodes, the pumping node is precharged to the same value at the pumping node in starting pumping. Since the first-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located in front of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with the conventional cross-coupled charge pump by using a stack-MIM capacitor. A proposed charge pump for TFT-LCD driver IC is designed with 0.13 µm triple-well DDI process, fabricated, and tested.

For battery-powered electronic products, one way to extend battery life is to use a versatile step-up/step-down DC-DC converter. A new versatile step-up/step-down switched-capacitor-based converter structure is proposed, and its efficiency is analyzed. In the step-down case, the efficiency is the same as, or even better than the efficiency of linear regulators.

This paper proposes novel feedforward architecture of the second-order multibit ΔΣAD modulator with single DAC-feedback topology. The ΔΣAD modulator realizes high resolution by oversampling and noise shaping techniques. However, its SNDR (Signal to Noise and Distortion Ratio) is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. A full feedforward ΔΣAD modulator structure has the signal transfer function of unity under ideal circumstances, which means that the signal swings through the loop filter become smaller compared with a feedbacked ΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced in the feedforward structure because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirements for amplifiers with low supply voltage. However, in conventional feedforward ΔΣAD modulator, an analog adder is needed before quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. We conducted MATLAB and SPICE simulations to validate the proposed architecture and modulator circuits.

Developing LSIs with EMI suppression, particularly for use in automobiles, is important for improving warranties and customer acquisition. First, we describe that the measures against EMI noise caused by a X'tal oscillator are important. Next, we present a practical method for analyzing the noise with models of the inside and outside of a chip. In addition, we propose a within-chip measure against EMI noise that takes chip cost into account. The noise is suppressed by using an appropriate resistance and capacitance on the power line. Simulation results demonstrated the method's effectiveness in suppressing noise.

The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique.

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

A sandwich structure type RF-MEMS variable capacitor is proposed, that consists of a movable middle plate, and fixed top and bottom plates having different areas. Simulation results show that the proposed capacitor can operate at a control voltage of less than 3.2 V; it achieves a tuning range of 4.8:1 (capacitance:630-130 fF) in the range of 0 to 3.2 V and at a frequency of 7.5 GHz.

Comb capacitors suitable for use in advanced complementary metal-oxide semiconductor (CMOS) technology nodes are frequently constructed from low metal layers located closely above the conductive silicon substrate. This results in high parasitic capacitances across the thin dielectric between the two layers. Therefore, a shield for reducing this parasitic capacitance is proposed in order to use the comb capacitor at high frequency. From electromagnetic (EM) simulation results using a 3D EM simulator, the quality factor (Q-factor) of the proposed shielded comb capacitor for the differential signal improved by 20% at 30-110 GHz compared to the unshielded capacitor. Consequently, a scalable model is proposed, which operates up to millimeter-wave frequencies. The results are verified by experimental data using fabricated comb capacitors from a 90 nm 1P9M CMOS process. Compared with the experimental results, the simulated common-mode and differential-mode S parameters of the model has a root-mean-square (r.m.s.) error of under 2.1%.

This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.

This paper presents an ultra-wideband (UWB) bandpass filter using a combination of broadside-coupled structure and lumped-capacitor-loaded shunt stub resonator. The broadside-coupled microstrip-to-coplanar waveguide structure provides an ultra-wide bandpass filtering operation and keeps a good stopband at lower frequencies from DC at the same time. The lumped-capacitor-loaded shunt stub resonator creates two transmission zeros (attenuation poles which can be located at the outsides of the two bandedges of the UWB bandpass filter to improve the out-band performance by selecting a suitable combination of the length of the shunt stubs and the capacitance of the loaded chip capacitors. The filter was designed based on electromagnetic simulation for broadside-coupled structure, microwave circuit simulation and experiments for determining the transmission zeros. The filter was fabricated on a one-layer dielectric substrate. The measured results demonstrated that the developed UWB bandpass filter has good performance: low insertion loss about 0.46 dB and low group delay about 0.26 ns at the center of the passband and very flat over the whole passband, and less than -10 dB reflection over the passband. The implemented transmission zeros, particularly at the low frequency end, dramatically improved the out-band performance, leading the filter satisfy the FCC's spectrum mask not only for indoor but also for outdoor applications. These poles improved also the skirt performance at both bandedges of the filter. A lowpass filter has been also introduced and integrated with the proposed bandpass filter to have a further improvement of the out-band performance at the high frequency end. The filters integrated with lowpass section exhibit excellent filter performance: almost satisfying the FCC's spectrum mask from DC to 18 GHz. The developed UWB bandpass filter has a compact size of 4 cm1.5 cm, or 4.8 cm1.5 cm with lowpass section implemented.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.

A 1-V operational sigma-delta modulator with a second-order passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.