Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.

We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications. To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation (PAM) 4 and wavelength-division-multiplexing technologies were also introduced to enhance the transmission capacity.

To address the bandwidth bottleneck that exists between LSI chips, we have proposed a novel, high-sensitivity receiver circuit for differential optical transmission on a silicon optical interposer. Both anodes and cathodes of the differential photodiodes (PDs) were designed to be connected to a transimpedance amplifier (TIA) through coupling capacitors. Reverse bias voltage was applied to each of the differential PDs through load resistance. The proposed receiver circuit achieved double the current signal amplitude of conventional differential receiver circuits. The frequency response of the receiver circuit was analyzed using its equivalent circuit, wherein the temperature dependence of the PD was implemented. The optimal load resistances of the PDs were determined to be 5kΩ by considering the tradeoff between the frequency response and bias voltage drop. A small dark current of the PD was important to reduce the voltage drop, but the bandwidth degradation was negligible if the dark current at room temperature was below 1µA. The proposed circuit achieved 3-dB bandwidths of 18.9 GHz at 25°C and 13.7 GHz at 85°C. Clear eye openings in the TIA output waveforms for 25-Gbps 27-1 pseudorandom binary sequence signals were obtained at both temperatures.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.

In this paper, we examined the transfer method of fluororesin as the novel formation method of polymer wall in order to realize the lattice-shaped polymer walls without patterned light irradiation using photomask. We clarified that the transfer method was effective for formation of polymer wall structure on flexible substrate.

A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.

Quadrant silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and were characterized at 405nm wavelength for Blu-ray applications. The size of each APD element is 50×50µm2. The dark current was 10pA at low bias voltage, and low crosstalk of about -80dB between adjacent APD elements was achieved. Although the responsivity is less than 0.1A/W at low bias voltage, the responsivity is enhanced to more than 1A/W at less than 10V bias voltage due to avalanche amplification. The wide bandwidth of 1.5GHz was achieved with the responsivity of more than 1A/W, which is limited by the capacitance of the APD. We believe that the fabricated quadrant APD is a promising photodiode for multi-layer Blu-ray system.

In the past decade, real-time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

To prepare antireflection coating (ARC) by wet process is important technology for low cost fabrication of solar cells. In this research, we consider the optical reflectance of a three layer stack structure of ARC films on the pyramidally textured single-crystalline silicon substrates. Each layer of the ARC films is deposited by a spin-coating method. The triple layers consist of SiO2, SiO2-TiO2 mixture, and TiO2 films from air to the silicon substrate in that order, and the refractive index is slightly increased from air to the substrate. Light reflection can be reduced further mainly due to graded index effect. The optimized three layer structure ARC shows that the reflectance is below 0.048 at the wavelength of 600 nm.

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Capability of SOTB to effectively reduce leakage by body biasing is fully exploited in BBS. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

We proposed the simulation method of reconstructed holographic images in considering phase distribution in the small pixels of liquid crystal spatial light modulator (LC-SLM) and clarified zero-order diffraction appeared on the reconstructed images when the phase distribution in a single pixel is non-uniform. These results are useful for design of fine LC-SLM for realizing wide-viewing-angle holographic displays.

We present dynamic mode switching characteristic by using a 2 × 2 optical mode switch based on silicon waveguide. The configuration of optical mode switch is similar to MZI where the width of input and output ports are designed to permit the combining of the fundamental mode and the first order mode. We designed the symmetrical arms with phase shifter based on p-i-n structure in one arm to generate a π-phase difference between each arm. As a result, mode switching with the injection current of 60mA (5.7V) was successfully achieved with the mode crosstalk of -10dB at λ=1550nm. A minimum of less than 60ns and 40ns mode switching time for the fundamental mode to first order mode and first order mode to fundamental mode, was achieved respectively in this time.

Silicon-on-insulator (SOI) has become one of the most famous materials in recent years, especially in silicon photonics applications. This paper presents a comparative performance of a SOI-based optical interconnect (OI) vs. an electrical interconnect (EI) for high-speed performances at a circuit level. The SOI-based optical waveguide was designed using OptiBPM to obtain a single mode condition (SMC). Then, the optical interconnect (OI) link was simulated in OptiSPICE and was tested as an interconnection in two-stage CS amplifiers. The results showed that the two-stage CS amplifier using OI offered several advantages in terms of electrical performances, such as voltage gain, frequency bandwidth, slew rate, and propagation delay, which makes it superior to the EI.

The electron retention characteristics of memory capacitors with blocking oxide-silicon carbonitride (SiCN)-tunnel oxide stacked films were investigated for application in embedded charge trapping nonvolatile memories (NVMs). Long-term data retention in the SiCN memory capacitors was estimated to be more than 10 years at 85 °C. We presented an improved method to analyze the energy distribution of electron trap states numerically. Using the presented analytical method, electron trap states in the SiCN film were revealed to be distributed from 0.8 to 1.3 eV below the conduction band edge in the SiCN band gap. The presence of energetically deep trap states leads us to suggest that the SiCN dielectric films can be employed as the charge trapping film of embedded NVMs.

In this paper, Epitaxial (Epi) Junction Termination Extension (JTE) technique for silicon carbide (SiC) power device is presented. Unlike conventional JTE, the Epi-JTE doesn't require high temperature (about 500°C) implantation process. Thus, it doesn't require high temperature (about 1700°C) process for implanted dose activation and surface defect curing. Therefore, the manufacturing cost will be decreased. Also, the fabrication process is very simple because the dose of the JTE is controlled by epitaxy growth. The blocking characteristic is analyzed through 2D-simulation for the proposed Epi-JTE. In addition, the effect was validated by experiment of fabricated SiC device with the Single-Zone-Epi-JTE. As a result, it has blocking capability of 79.4% compared to ideal parallel-plane junction breakdown.

We have developed membrane distributed Bragg reflector (DBR) lasers on thermally oxidized Si substrate (SiO2/Si substrate) to evaluate the parameters of the on-Si lasers we have been developing. The lasers have InGaAsP-based multi-quantum wells (MQWs) grown on InP substrate. We used direct bonding to transfer this active epitaxial layer to SiO2/Si substrate, followed by epitaxial growth of InP to fabricate a buried-heterostructure (BH) on Si. The lateral p-i-n structure was formed by thermal diffusion of Zn and ion implantation of Si. For the purpose of evaluating laser parameters such as internal quantum efficiency and internal loss, we fabricated long-cavity lasers that have 200- to 600-µm-long active regions. The fabricated DBR lasers exhibit threshold currents of 1.7, 2.1, 2.8, and 3.7mA for active-region lengths of 200, 300, 400, and 600µm, respectively. The differential quantum efficiency also depends on active-region length. In addition, the laser characteristics depend on the distance between active region and p-doped region. We evaluated the internal loss to be 10.2cm-1 and internal quantum efficiency to be 32.4% with appropriate doping profile.

We prepared alumina passivation films for p-type silicon substrates by sol-gel wet process mainly using aluminum isopropoxide (Al(O-i-Pr)3) as a precursor material. The precursor solution was spin-coated onto p-type silicon substrates and then calcined for 1 hour in air. Minority carrier lifetime of the passivated wafers was evaluated for different calcination temperature conditions. We also compared the passivation quality of the alumina passivation films using different alumina precursor, aluminum acetylacetonate (Al(acac)3). Obtained effective minority carrier lifetime indicated that the lifetime is strongly depends on the calcination temperature. The substrate calcined below 400°C shows relatively short lifetime below 100 µsec. On the other hand, the substrate calcined around 500°C to 600°C indicates lifetime from 250 to 300 µsec. Calcination temperature dependence of the lifetime for the samples using Al(O-i-Pr)3 precursors shows almost the same as that using Al(acac)3.

We fabricated silicon solar cells with spin-coated sol-gel alumina passivation layers on the rear side. Spin-coated alumina passivation films have moderate passivation quality and are inferior to atomic layer deposited passivation films. However, low-cost and low temperature process of the sol-gel deposition is still beneficial for the cells using commercially available Cz silicon wafers. Thus, we consider an applicability of the spin-coated alumina passivation layer for rear side passivation. Dependence of cell efficiency on contact spacing and contact diameter of a rear electrode was investigated by both experiments and numerical calculation. The experimental results indicated that conversion efficiency of the cell is enhanced from 9.1% to 11.1% by optimizing an aperture ratio and contact spacing of the rear passivation layers. Numerical calculation indicated that small contact diameter with low aperture ratio of a rear passivation layer is preferable to achieve good cell performance in our experimental condition. We confirmed the effectivity of the spin-coated alumina passivation films for rear surface passivation of the low-cost silicon solar cells.

nMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84µm, the detection area of 10×10µm2, the PAD size for RF probing of 30×30µm2, and with the guard ring structure. The maximum bandwidth of 8.4GHz was achieved along with the gain-bandwidth product of 280GHz.

We have proposed and demonstrated the principle of optical mode switch. However, the crosstalk between modes has not yet reported due to the difficulty of mode recognition and distinction. To accomplish this mode crosstalk evaluation, we integrated multimode interference (MMI) mode filter with the optical mode switch in this work. As a result, for the both TE and TM modes, the crosstalk of approximately -10 dB has been evaluated experimentally.