The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.

A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

A data analysis technology of atomic force microscopy for atomically flat silicon surfaces has been developed. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200 mm diameter wafers by annealing in pure argon ambience at 1,200 for 30 minutes. Atomically flat silicon surfaces are lead to improve the MOS inversion layer mobility and current drivability of MOSFETs and to decrease the fluctuations in electrical characteristics of MOSFETs. It is important to realize the technology that evaluates the flatness and the uniformity of atomically flat silicon surfaces. The off direction angle is calculated by using two straight edge lines selected from measurement data. And the off angle is calculated from average atomic terrace width under assumption that height difference between neighboring terraces is equal to the step height, 0.135 nm, of (100) silicon surface. The analyzing of flatness of each terrace can be realized by converting the measurement data using the off direction angle and the off angle. And, the average roughness of each terrace is about 0.017-0.023 nm. Therefore, the roughness and the uniformity of each terrace can be evaluated by this proposed technique.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

Silicon photonic devices based on silicon photonic wire waveguides are especially attractive devices, since they can be ultra-compact and low-power consumption. In this paper, we demonstrated various devices fabricated on silicon photonic wire waveguides. They included optical directional couplers, reconfigurable optical add/drop multiplexers, 12, 14, 18 and 44 optical switches, ring resonators. The characteristics of these devices show that silicon photonic wire waveguides offer promising platforms in constructing compact and power-saving photonic devices and systems.

A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.

In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.

Characteristics of conductive elastomer that is composed of silicone rubber and dispersed carbon black particles show conductive and elastic properties in one simple material. This material has been widely applied to make-break contacts of panel switches and connectors of liquid crystal panels. However, since surface state of the contact is very soft, it is difficult to remove contaminant films of contaminated opposite side contact surface and to obtain low contact resistance owing to break the film. This is an important problem to be solved not only for the application of make-break switching contact but also static connector contacts. This study has been conducted to examine some complex structures of the elastomer which indicate removal characteristics for contaminant films and low contact resistance. As specimens, six different types of elastomer contacts composed of different type of dispersed materials as carbon and metal fibers, metal mesh, and plated surfaces were used. The contacts of opposite side were Au and Sn plated contact surface on a printed circuit board (PCB) which is usually used in the static connector and make-break contacts. In order to contaminate contact surfaces of PCB, the surfaces were subjected to exposure in an SO2 gas environment. The elastomeric contacts contained hard materials showed lower contact resistance than only dispersed carbon particles in the elastomer matrix for both contaminated PCB contact surfaces.

With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESD-protected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well.

This paper will review the development of SiC power devices especially SiC power junction field-effect transistors (JFETs). Rationale and different approaches to the development of SiC power JFETs will be presented, focusing on normally-OFF power JFETs that can provide the highly desired fail-save feature for reliable power switching applications. New results for the first demonstration of SiC Power ICs will be presented and the potential for distributed DC-DC power converters at frequencies higher than 35 MHz will be discussed.

Millimeter-waves integrated circuits offer a unique opportunity for a holistic design approach encompassing RF, analog, and digital, as well as radiation and electromagnetics. The ability to deal with the complete system covering a broad range from the digital circuitry to on-chip antennas and everything in between offers unparalleled opportunities for completely new architectures and topologies, which were previously impossible due the traditional partitioning of various blocks in conventional design. This can open a plethora of new architectural and system level innovation within the integrated circuit platform. This paper reviews some of the challenges and opportunities for mm-wave ICs and presents several solutions to them.

We propose and demonstrate a simple one-bus two-ring configuration where the two rings are mutually coupled that has advantages over the one-ring structure. Unlike a one cavity system, it can exhibit near critically-coupled transmission with a broader range of loss. It can also significantly enhance the cavity finesse by simply making the second ring twice the size of the bus-coupled one, with the enhancement proportional to the intensity buildup in the second ring.

The historical review of Taiwan's researching activities on the features of PECVD grown SiOx are also included to realize the performance of Si nanocrystal based MOSLED made by such a Si-rich SiOx film with embedded Si nanocrystals on conventional Si substrate. A surface nano-roughened Si substrate with interfacial Si nano-pyramids at SiOx/Si interface are also reviewed, which provide the capabilities of enhancing the surface roughness induced total-internal-reflection relaxation and the Fowler-Nordheim tunneling based carrier injection. These structures enable the light emission and extraction from a metal-SiOx-Si MOSLED.

This paper reviews recent world-wide progress in silicon-based photonics-and-optoelectronics in order to provide a context for the papers in this special section of the IEICE Transactions. The impact of present and potential applications is discussed.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

In this letter, the fabrication of a compact and high performance semi-lumped coplanar waveguide low-pass filter (CPW-LPF) on high resistivity silicon (HRS) substrate at millimeter wave is proposed. The design procedure and the equivalent circuit of the proposed semi-lumped CPW-LPF is discussed. The filter structure of is very simple but its performances is fairly good. This designed filter at cutoff frequency fc of 31 GHz has very good measured characteristics including the low insertion loss, sharp rejection and low group delay, due to the reduced substrate loss of HRS. Experimental results of the fabricated filter show a good agreement with the predicted results.

The physical origin of stress-induced leakage currents (SILC) in ultra-thin SiO2 films is described. Assuming a two-step trap-assisted tunneling process accompanied with an energy relaxation process of trapped electrons, conditions of trap sites which are origin of SICL are quantitatively found. It is proposed that the trap site location and the trap state energy can be explained by a mean-free-path of hole in SiO2 films and an atomic structure of the trap site by the O vacancy model.

Novel functionality and material were developed for Si-photonics in this study. Ultra-fast silicon all optical switches using two-photon absorption (TPA) were developed in silicon nanowire optical waveguide on silicon-on-insulator substrate. This waveguide can produce high optical intensities that yield optical nonlinearity such as TPA even at input optical powers typically used in fiber optic communication systems. In addition, we fabricated a GaSb based quantum well (QW) on a Si substrate. The emission wavelength of QW was 1.55 µm at room temperature, so that the new function can be developed on Si-photonics using this QW.

A lithium niobate (LiNbO3)/silicon (Si) hybrid structure has been developed by the surface-activated bonding of LiNbO3 chips with gold (Au) thin film to Si substrates with patterned Au film. After organic contaminants on the Au surfaces were removed using argon radio-frequency plasma, Au-to-Au bonding was carried out in ambient air. Strong bonding at significantly low temperatures below 100 without generating cracks has been demonstrated.

In this study, a cascade open-short-thru (COST) de-embedding procedure is proposed for the first time for on-wafer device characterization in the RF/microwave frequency regime. This technique utilizes the "open" and "short" dummy structures to de-embed the probe-pad parasitics of a device-under-test (DUT). Furthermore, to accurately estimate the input/output interconnect parasitics, including the resistive, inductive, capacitive, and conductive components, the "thru" dummy device has been characterized after probe-pad de-embedding. With the combination of transmission-line theory and cascade-configuration concept, this method can efficiently generate the scalable and repeatable interconnect parameters to completely eliminate the redundant parasitics of the active/passive DUTs of various device sizes and interconnect dimensions. Consequently, this method is very suitable for the on-wafer automatic measurement.