A channel coding problem with cost constraint for general channels is considered. Verdú and Han derived ϵ-capacity for general channels. Following the same lines of its proof, we can also derive ϵ-capacity with cost constraint. In this paper, we derive a formula for ϵ-capacity with cost constraint allowing overrun. In order to prove this theorem, a new variation of Feinstein's lemma is applied to select codewords satisfying cost constraint and codewords not satisfying cost constraint.

Distributed computing is one of the powerful solutions for computational tasks that need the massive size of dataset. Lagrange coded computing (LCC), proposed by Yu et al. [15], realizes private and secure distributed computing under the existence of stragglers, malicious workers, and colluding workers by using an encoding polynomial. Since the encoding polynomial depends on a dataset, it must be updated every arrival of new dataset. Therefore, it is necessary to employ efficient algorithm to construct the encoding polynomial. In this paper, we propose Newton coded computing (NCC) which is based on Newton interpolation to construct the encoding polynomial. Let K, L, and T be the number of data, the length of each data, and the number of colluding workers, respectively. Then, the computational complexity for construction of an encoding polynomial is improved from O(L(K+T)log 2(K+T)log log (K+T)) for LCC to O(L(K+T)log (K+T)) for the proposed method. Furthermore, by applying the proposed method, the computational complexity for updating the encoding polynomial is improved from O(L(K+T)log 2(K+T)log log (K+T)) for LCC to O(L) for the proposed method.

In this work we propose a Bayesian version of the Nagaoka-Hayashi bound when estimating a parametric family of quantum states. This lower bound is a generalization of a recently proposed bound for point estimation to Bayesian estimation. We then show that the proposed lower bound can be efficiently computed as a semidefinite programming problem. As a lower bound, we also derive a Bayesian version of the Holevo-type bound from the Bayesian Nagaoka-Hayashi bound. Lastly, we prove that the new lower bound is tighter than the Bayesian quantum logarithmic derivative bounds.

Approximate computing (AC) saves energy and improves performance by introducing approximation into computation in error-torrent applications. This work focuses on an AC strategy that accurately performs important computations and approximates others. In order to make AC circuits practical, we need to determine which computation is how important carefully, and thus need to appropriately approximate the redundant computation for maintaining the required computational quality. In this paper, we focus on the importance of computations at the flip-flop (FF) level and propose a novel importance evaluation methodology. The key idea of the proposed methodology is a two-step fault injection algorithm to extract the near-optimal set of redundant FFs in the circuit. In the first step, the proposed methodology performs the FI simulation for each FF and extracts the candidates of redundant FFs. Then, in the second step, the proposed methodology extracts the set of redundant FFs in a binary search manner. Thanks to the two-step strategy, the proposed algorithm reduces the complexity of architecture exploration from an exponential order to a linear order without understanding the functionality and behavior of the target application program. Experimental results show that the proposed methodology identifies the candidates of redundant FFs depending on the given constraints. In a case study of an image processing accelerator, the truncation for identified redundant FFs reduces the circuit area by 29.6% and saves power dissipation by 44.8% under the ASIC implementation while satisfying the PSNR constraint. Similarly, the dynamic power dissipation is saved by 47.2% under the FPGA implementation.

In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

Aiming at the problem of “energy hole” caused by random distribution of nodes in large-scale wireless sensor networks (WSNs), this paper proposes an adaptive energy-efficient balanced uneven clustering routing protocol (AEBUC) for WSNs. The competition radius is adaptively adjusted based on the node density and the distance from candidate cluster head (CH) to base station (BS) to achieve scale-controlled adaptive optimal clustering; in candidate CHs, the energy relative density and candidate CH relative density are comprehensively considered to achieve dynamic CH selection. In the inter-cluster communication, based on the principle of energy balance, the relay communication cost function is established and combined with the minimum spanning tree method to realize the optimized inter-cluster multi-hop routing, forming an efficient communication routing tree. The experimental results show that the protocol effectively saves network energy, significantly extends network lifetime, and better solves the “energy hole” problem.

Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.

Song-level feature summarization is fundamental for the browsing, retrieval, and indexing of digital music archives. This study proposes a deep neural network model, CQTXNet, for extracting song-level feature summary for cover song identification. CQTXNet incorporates depth-wise separable convolution, residual network connections, and attention models to extend previous approaches. An experimental evaluation of the proposed CQTXNet was performed on two publicly available cover song datasets by varying the number of network layers and the type of attention modules.

This paper proposes a novel application of coded apertures (CAs) for visual information hiding. CA is one of the representative computational photography techniques, in which a patterned mask is attached to a camera as an alternative to a conventional circular aperture. With image processing in the post-processing phase, various functions such as omnifocal image capturing and depth estimation can be performed. In general, a watermark embedded as high-frequency components is difficult to extract if captured outside the focal length, and defocus blur occurs. Installation of a CA into the camera is a simple solution to mitigate the difficulty, and several attempts are conducted to make a better design for stable extraction. On the contrary, our motivation is to design a specific CA as well as an information hiding scheme; the secret information can only be decoded if an image with hidden information is captured with the key aperture at a certain distance outside the focus range. The proposed technique designs the key aperture patterns and information hiding scheme through evolutionary multi-objective optimization so as to minimize the decryption error of a hidden image when using the key aperture while minimizing the accuracy when using other apertures. During the optimization process, solution candidates, i.e., key aperture patterns and information hiding schemes, are evaluated on actual devices to account for disturbances that cannot be considered in optical simulations. Experimental results have shown that decoding can be performed with the designed key aperture and similar ones, that decrypted image quality deteriorates as the similarity between the key and the aperture used for decryption decreases, and that the proposed information hiding technique works on actual devices.

Device-to-device (D2D) communication allows user terminals to directly communicate with each other without the need for any base stations (BSs). Since the D2D communication underlaying a cellular system shares frequency channels with BSs, co-channel interference may occur. Successive interference cancellation (SIC), which is also called the serial interference canceler, detects and subtracts user signals from received signals in descending order of received power, can cope with the above interference and has already been applied to fog nodes that manage communications among machine-to-machine (M2M) devices besides direct communications with BSs. When differences among received power levels of user signals are negligible, however, SIC cannot work well and thus causes degradation in bit error rate (BER) performance. To solve such a problem, this paper proposes to apply parallel interference cancellation (PIC), which can simultaneously detect both desired and interfering signals under the maximum likelihood criterion and can maintain good BER performance even when power level differences among users are small. When channel coding is employed, however, SIC can be superior to PIC in terms of BER under some channel conditions. Considering the superiority, this paper also proposes to select the proper cancellation scheme and modulation and coding scheme (MCS) that can maximize the throughput of D2D under a constraint of BER, in which the canceler selection is referred to as adaptive interference cancellation. Computer simulations show that PIC outperforms SIC under almost all channel conditions and thus the adaptive selection from PIC and SIC can achieve a marginal gain over PIC, while PIC can achieve 10% higher average system throughput than that of SIC. As for transmission delay time, it is demonstrated that the adaptive selection and PIC can shorten the delay time more than any other schemes, although the fog node causes the delay time of 1ms at least.

In the beyond 5G and 6G networks, the number of connected devices and their types will greatly increase including not only user devices such as smartphones but also the Internet of Things (IoT). Moreover, Non-terrestrial networks (NTN) introduce dynamic changes in the types of connected devices as base stations or access points are moving objects. Therefore, continuous network capacity design is required to fulfill the network requirements of each device. However, continuous optimization of network capacity design for each device within a short time span becomes difficult because of the heavy calculation amount. We introduce device types as groups of devices whose traffic characteristics resemble and optimize network capacity per device type for efficient network capacity design. This paper proposes a method to classify device types by analyzing only encrypted traffic behavior without using payload and packets of specific protocols. In the first stage, general device types, such as IoT and non-IoT, are classified by analyzing packet header statistics using machine learning. Then, in the second stage, connected devices classified as IoT in the first stage are classified into IoT device types, by analyzing a time series of traffic behavior using deep learning. We demonstrate that the proposed method classifies device types by analyzing traffic datasets and outperforms the existing IoT-only device classification methods in terms of the number of types and the accuracy. In addition, the proposed model performs comparable as a state-of-the-art model of traffic classification, ResNet 1D model. The proposed method is suitable to grasp device types in terms of traffic characteristics toward efficient network capacity design in networks where massive devices for various services are connected and the connected devices continuously change.

An output voltage estimation and regulation system for a wireless power transfer (WPT) circuit is proposed. Since the fluctuation of a coupling condition and/or a load may vary the voltage supplied with WPT resulting in a malfunction of wireless-powered devices, the output voltage regulation is needed. If the output voltage is regulated by a voltage regulator in a secondary side of the WPT circuit with fixed input power, the voltage regulator wastes the power to regulate the voltage. Therefore the output voltage regulation using a primary-side control, which adjusts the input power depending on the load and/or the coupling condition, is a promising approach for efficient regulation. In addition, it is desirable to eliminate feedback loop from the secondary side to the primary side from the viewpoint of reducing power dissipation and system complexity. The proposed system can estimate and regulate the output voltage independent of both the coupling and the load variation without the feedback loop. An usable range of the coupling coefficient and the load is improved compared to previous works. The validity of the proposed system is confirmed by the SPICE simulator.

Statistical wafer-level characteristic variation modeling offers an attractive method for reducing the measurement cost in large-scale integrated (LSI) circuit testing while maintaining test quality. In this method, the performance of unmeasured LSI circuits fabricated on a wafer is statistically predicted based on a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in the wafers. However, actual wafers can exhibit discontinuous variations that are systematically caused by the manufacturing environment, such as shot dependence. In this paper, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into systematic discontinuous and global components to improve estimation accuracy. An evaluation performed using an industrial production test dataset indicates that the proposed method effectively reduces the estimation error for an entire wafer by over 36% compared with conventional methods.

We evaluated the transmission performance, including received power and transmission throughput characteristics, in 4×4 single-user multiple-input multiple-output (SU-MIMO) transmission for synchronous time division duplex (TDD) and downlink data channels in comparison with single-input single-output (SISO) transmission in an environment where a local 5G wireless base station was installed on the roof of a research building at our university. Accordingly, for the received power characteristics, the difference between the simulation value, which was based on the ray tracing method, and the experimental value at 32 points in the area was within a maximum difference of approximately 10 dB, and sufficient compliance was obtained. Regarding the transmission throughput versus received power characteristics, after showing a simulation method for evaluating throughput characteristics in MIMO, we compared the results with experimental results. The cumulative distribution function (CDF) of the transmission throughput shows that, at a CDF of 50%, in SISO transmission, the simulated value is approximately 115Mbps, and the experimental value is 105Mbps, within a difference of approximately 10Mbps. By contrast, in MIMO transmission, the simulation value is 380Mbps, and the experimental value is approximately 420Mbps, which is a difference of approximately 40Mbps. It was shown that the received power and transmission throughput characteristics can be predicted with sufficient accuracy by obtaining the delay profile and the system model at each reception point using the both ray tracing and MIMO simulation methods in actual environments.

A group signature scheme allows us to anonymously sign a message on behalf of a group. One of important issues in the group signatures is user revocation, and thus lots of revocable group signature (RGS) schemes have been proposed so far. One of the applications suitable to the group signature is privacy-enhancing crowdsensing, where the group signature allows mobile sensing users to be anonymously authenticated to hide the location. In the mobile environment, verifier-local revocation (VLR) type of RGS schemes are suitable, since revocation list (RL) is not needed in the user side. However, in the conventional VLR-RGS schemes, the revocation check in the verifier needs O(R) cryptographic operations for the number R of revoked users. On this background, VLR-RGS schemes with efficient revocation check have been recently proposed, where the revocation check is just (bit-string) matching. However, in the existing schemes, signatures are linkable in the same interval or in the same application-independent task with a public index. The linkability is useful in some scenarios, but users want the unlinkability for the stronger anonymity. In this paper, by introducing a property that at most K unlinkable signatures can be issued by a signer during each interval for a fixed integer K, we propose a VLR-RGS scheme with the revocation token matching. In our scheme, even the signatures during the same interval are unlinkable. Furthermore, since used indexes are hidden, the strong anonymity remains. The overheads are the computational costs of the revocation algorithm and the RL size. We show that the overheads are practical in use cases of crowdsensing.

With the rapid developments in the Internet of Things (IoT), low power wide area networks (LPWAN) framework, which is a low-power, long-distance communication method, is attracting attention. However, in LPWAN, the access time is limited by Duty Cycle (DC) to avoid mutual interference. Packet-level index modulation (PLIM) is a modulation scheme that uses a combination of the transmission time and frequency channel of a packet as an index, enabling throughput expansion even under DC constraints. The indexes used in PLIM are transmitted according to the mapping. However, when many sensors access the same index, packet collisions occur owing to selecting the same index. Therefore, we propose a mapping design for PLIM using mathematical optimization. The mapping was designed and modeled as a quadratic integer programming problem. The results of the computer simulation evaluations were used to realize the design of PLIM, which achieved excellent sensor information aggregation in terms of environmental monitoring accuracy.

As more and more programs handle personal information, the demand for secure handling of data is increasing. The protocol that satisfies this demand is called Secure function evaluation (SFE) and has attracted much attention from a privacy protection perspective. In two-party SFE, two mutually untrustworthy parties compute an arbitrary function on their respective secret inputs without disclosing any information other than the output of the function. For example, it is possible to execute a program while protecting private information, such as genomic information. The garbled circuit (GC) — a method of program obfuscation in which the program is divided into gates and the output is calculated using a symmetric key cipher for each gate — is an efficient method for this purpose. However, GC is computationally expensive and has a significant overhead even with an accelerator. We focus on hardware acceleration because of the nature of GC, which is limited to certain types of calculations, such as encryption and XOR. In this paper, we propose an architecture that accelerates garbling by running multiple garbling engines simultaneously based on the latest FPGA-based GC accelerator. In this architecture, managers are introduced to perform multiple rows of pipeline processing simultaneously. We also propose an optimized implementation of RAM for this FPGA accelerator. As a result, it achieves an average performance improvement of 26% in garbling the same set of programs, compared to the state-of-the-art (SOTA) garbling accelerator.

Person authentication using biometric information has recently become popular among researchers. User management based on biometrics is more reliable than that using conventional methods. To secure private information, it is necessary to build continuous authentication-based user management systems. Brain waves are suitable biometric modalities for continuous authentication. This study is based on biometric authentication using brain waves evoked by invisible visual stimuli. Invisible visual stimulation is considered over visual stimulation to overcome the obstacles faced by a user when using a system. Invisible stimuli are confirmed by changing the intensity of the image and presenting high-speed stimulation. To ensure invisibility, stimuli of different intensities were tested, and the stimuli with an intensity of 5% was confirmed to be invisible. To improve the verification performance, a continuous wavelet transform was introduced over the Fourier transform because it extracts both time and frequency information from the brain wave. The scalogram obtained by the wavelet transform was used as an individual feature and for synchronizing the template and test data. Furthermore, to improve the synchronization performance, the waveband was split based on the power distribution of the scalogram. A performance evaluation using 20 subjects showed an equal error rate of 3.8%.

Advanced driver-assistance systems (ADAS) generally play an important role to support safe drive by detecting potential risk factors beforehand and informing the driver of them. However, if too many services in ADAS rely on visual-based technologies, the driver becomes increasingly burdened and exhausted especially on their eyes. The drivers should be back out of monitoring tasks other than significantly important ones in order to alleviate the burden of the driver as long as possible. In-vehicle auditory signals to assist the safe drive have been appealing as another approach to altering visual suggestions in recent years. In this paper, we developed an in-vehicle auditory signals evaluation platform in an existing driving simulator. In addition, using in-vehicle auditory signals, we have demonstrated that our developed platform has highlighted the possibility to partially switch from only visual-based tasks to mixing with auditory-based ones for alleviating the burden on drivers.

In this paper, a circuit based on a field programmable analog array (FPAA) is proposed for three types of chaotic spiking oscillator (CSO). The input/output conversion characteristics of a specific element in the FPAA can be defined by the user. By selecting the proper characteristics, three types of CSO are realized without changing the structure of the circuit itself. Chaotic attractors are observed in a hardware experiment. It is confirmed that the dynamics of the CSOs are consistent with numerical simulations.