In this paper, a balance operation Transimpedance Amplifier (TIA) with low-noise has been implemented for optical receivers in 130 nm SiGe BiCMOS Technology, in which the optimal tradeoff emitter current density and the location of high-frequency noise corner were analyzed for acquiring low-noise performance. The Auto-Zero Feedback Loop (AZFL) without introducing unnecessary noises at input of the TIA, the tail current sink with high symmetries and the balance operation TIA with the shared output of Operational Amplifier (OpAmp) in AZFL were designed to keep balanced operation for the TIA. Moreover, cascode and shunt-feedback were also employed to expanding bandwidth and decreasing input referred noise. Besides, the formula for calculating high-frequency noise corner in Heterojunction Bipolar Transistor (HBT) TIA with shunt-feedback was derived. The electrical measurement was performed to validate the notions described in this work, appearing 9.6 pA/√Hz of input referred noise current Power Spectral Density (PSD), balance operation (VIN1=896mV, VIN2=896mV, VOUT1=1.978V, VOUT2=1.979V), bandwidth of 32GHz, overall transimpedance gain of 68.6dBΩ, a total 117mW power consumption and chip area of 484µm × 486µm.

This paper presents a wideband inductorless noise-cancelling balun LNA with two gain modes, low NF, and high-linearity for LTE and intermediate-frequency-band (eg. 3.3-3.6GHz, 4.8-5GHz) 5G applications fabricated in 65nm CMOS. The proposed LNA is bonding tested and exhibits a minimum NF of 2.2dB and maximum IIP3 of -3.5dBm. Taking advantage of an off-chip bias inductor in CG stage and a cross-coupled buffer, the LNA occupies high operation frequency up to 5GHz with remarkable linearity and NF as well as compact area.

A wideband CMOS common-gate low-noise amplifier (LNA) with high linearity is proposed. The linearity is improved by dual cross-coupled feedback technique. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3), which is known as one of the limitations for linearity enhancement using feedback. An active cross-coupled feedback, constituted by a voltage combiner and a feedback capacitor is employed to enhance loop gain, and acquire further linearity improvement. An enhanced LC-match input network and forward isolation of active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance. Fabricated in a 0.13 µm RF CMOS process, the LNA achieves a flat voltage gain of 13 dB, an NF of 2.6∼3.8 dB, and an IIP3 of 3.6∼4.9 dBm over a 3 dB bandwidth of 0.1∼1.3 GHz. It consumes only 3.2 mA from a 1.2 V supply and occupies an area of 480×418 um2. In contrast to those of reported wideband LNAs, the proposed LNA has the merit of low power consumption and high linearity.

We propose a low-noise and low-power dynamic comparator with an offset calibration circuit for Low-Power ADCs. The proposed comparator equips the control circuit in order to switching the comparison accuracy and the current consumption. When high accuracy is not required, current consumption is reduced by allowing the noise increase. Compared with a traditional dynamic comparator, the proposed architecture reduced the current consumption to 78% at 100MHz operating and 1.8V supply voltage. Furthermore, the offset voltage is corrected with minimal current consumption by controlling the on/off operation of the offset calibration circuit.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

Recent attempts to directly combine CMOS pixel readout chips with modern gas detectors open the possibility to fully take advantage of gas detectors. Those conventional readout LSIs designed for hybrid semiconductor detectors show some issues when applied to gas detectors. Several new proposed readout LSIs can improve the time and the charge measurement precision. However, the widely used basic charge sensitive amplifier (CSA) has an almost fixed dynamic range. There is a trade-off between the charge measurement resolution and the detectable input charge range. This paper presents a method to apply the folding integration technique to a basic CSA. As a result, the detectable input charge dynamic range is expanded while maintaining all the key merits of a basic CSA. Although folding integration technique has already been successfully applied in CMOS image sensors, the working conditions and the signal characteristics are quite different for pixel readout LSIs for gas particle detectors. The related issues of the folding CSA for pixel readout LSIs, including the charge error due to finite gain of the preamplifier, the calibration method of charge error, and the dynamic range expanding efficiency, are addressed and analyzed. As a design example, this paper also demonstrates the application of the folding integration technique to a Qpix readout chip. This improves the charge measurement resolution and expands the detectable input dynamic range while maintaining all the key features. Calculations with SPICE simulations show that the dynamic range can be improved by 12 dB while the charge measurement resolution is improved by 10 times. The charge error during the folding operation can be corrected to less than 0.5%, which is sufficient for large input charge measurement.

This paper presents a response time acceleration technique in a high-gain capacitive-feedback frontend amplifier (FA) for high output impedance sensors. Using an auxiliary amplifier as a unity-gain buffer, a sample-and-hold capacitor which is used for band-limiting and sampling the FA output is driven at the beginning of the transient response to make the response faster and then it is re-charged directly by the FA output. A condition and parameters for the response time acceleration using this technique while maintaining the noise level unaffected are discussed. Theoretical analysis and simulation results show that the response time can be less than half of the case without the acceleration technique for the specified settling error of less than 0.5%.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

This paper presents a single-chip RF tuner/OFDM demodulator for a mobile digital TV application called “1-segment broadcasting.” To achieve required performances for the single-chip receiver, a tunable technique for a low-noise amplifier (LNA) and spurious suppression techniques are proposed in this paper. Firstly, to receive all channels from 470 MHz to 770 MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, a tunable technique for the LNA is proposed. Then, to improve the sensitivity, spurious signal suppression techniques are also proposed. The single-chip receiver using the proposed techniques is fabricated in 90 nm CMOS technology and total die size is 3.26 mm 3.26 mm. Using the tunable LNA and suppressing undesired spurious signals, the sensitivities of less than -98.6 dBm are achieved for all the channels.

We propose a new parameter-extraction approach based on a mixed-mode genetic algorithm (GA), including the efficient search-space separation and local-minima-convergence prevention process. The technique, substantially extended from our previous work, allows the designed figures-of-merit, such as internal quantum efficiency (ηi) as well as transparency current density (Jtr) of lasers and minimum noise figure (NFmin) as well as associated available gain (GA,assoc) of low-noise amplifiers (LNAs), extracted by an analytical equation-based methodology combined with an evolutionary numerical tool. Extraction results, which agree well with actually measured data, for both state-of-the-art InGaAs quantum-well lasers and advanced SiGe LNAs are presented for the first time to demonstrate this multi-parameter analysis and high-accuracy optimization.

Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90 nm digital CMOS process. It occupies 0.12 mm2 and achieves |S11|<-10 dB, NF<4.4 dB, and |S21|>9.3 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0 V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 µm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48-860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm2.

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

Since a receiver (RX) and a transmitter (TX) are operated simultaneously in a WCDMA transceiver, noise and intermodulation distortion performances of a low-noise amplifier (LNA) are degraded by a large leakage signal from the TX. The degradation of the distortion due to the large leakage signal from the TX has been reported in some previous works, but to our best knowledge, there are no reports about the degradation of noise figure (NF) in a LNA due to the large leakage signal from the TX. In this paper, a 900-MHz LNA for WCDMA terminal with high tolerance for a leakage signal from the TX is proposed. Suitable designs of an input matching circuit and a trap circuit are adopted to improve the tolerance for the leakage signal from the TX. The LNA using the proposed techniques is fabricated using SiGe-BiCMOS process. The measured degradation of NF due to the leakage signal from the TX is suppressed to only 0.12 dB.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

In this study, an improved heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) active mixer is designed and fabricated. The HBT MMIC active mixer that is integrated with a low-noise amplifier (LNA) and active power adder can not only achieve high isolation, but can also dispense with one active component and reduce power consumption at the same time. Measurement results show that the conversion gain, LO-RF isolation, and double sideband noise figure (DSB-NF) of the proposed mixer are 22 dB, 40 dB, and 7 dB, respectively.