In this study, we introduce a lateral electric-field driving system based on continuous potential-difference driving using lateral transparent electrodes to achieve a wide viewing zone angle in electronic holographic displays. We evaluate light modulation to validate the independent driving capability of each pixel at a high resolution (pixel pitch: 1 μm). Additionally, we demonstrate the feasibility of two-dimensional driving by integrating the driving and ground electrodes.

The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate for tackling the issue due to its ultra-low latency, high bandwidth, and low power characteristics. Although previous research develops hardware accelerators by exploiting nanophotonic circuits for AI inference applications, there has never been considered for the acceleration of training that requires complex Floating-Point (FP) operations. In particular, the design balance between optical and electrical circuits has a critical impact on the latency, energy, and accuracy of the arithmetic system, and thus requires careful consideration of the optimal design. In this study, we design three types of Opto-Electrical Floating-point Multipliers (OEFMs): accuracy-oriented (Ao-OEFM), latency-oriented (Lo-OEFM), and energy-oriented (Eo-OEFM). Based on our evaluation, we confirm that Ao-OEFM has high noise resistance, and Lo-OEFM and Eo-OEFM still have sufficient calculation accuracy. Compared to conventional electrical circuits, Lo-OEFM achieves an 87% reduction in latency, and Eo-OEFM reduces energy consumption by 42%.

Wide deployment of artificial intelligence (AI) is inducing exponentially growing energy consumption. Traditional digital platforms are becoming difficult to fulfill such ever-growing demands on energy efficiency as well as computing latency, which necessitates the development of high efficiency analog hardware platforms for AI. Recently, optical and electrooptic hybrid computing is reactivated as a promising analog hardware alternative because it can accelerate the information processing in an energy-efficient way. Integrated photonic circuits offer such an analog hardware solution for implementing photonic AI and machine learning. For this purpose, we proposed a photonic analog of support vector machine and experimentally demonstrated low-latency and low-energy classification computing, which evidences the latency and energy advantages of optical analog computing over traditional digital computing. We also proposed an electrooptic Hopfield network for classifying and recognizing time-series data. This paper will review our work on implementing classification computing and Hopfield network by leveraging silicon photonic circuits.

A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

Quadrature phase-shift keying (QPSK) and 16-quadrature amplitude modulation (16QAM) formats are deployed in inter-data center networks where high transmission capacity and spectral efficiency are required. However, in intra-data center networks, a four-level pulse amplitude modulation (PAM4) format is deployed to satisfy the requirements for a simple and low-cost transceiver configuration. For the seamless and effective connection of such heterogeneous networks without an optical-electrical-optical conversion, an all-optical modulation format conversion technique is required. In this paper, we propose all-optical PAM4 to QPSK and 16QAM modulation format conversions using silicon-rich nitride waveguides. The successful conversions from 50-Gbps-class PAM4 signals to 50-Gbps-class QPSK and 100-Gbps-class 16QAM signals are demonstrated via numerical simulations.

We propose a novel silicon diplexer integrated with filters for frequency-division multiplexing in the 300-GHz band. The diplexer consists of a directional coupler formed of unclad silicon wires, a photonic bandgap-based low-pass filter, and a high-pass filter based on frequency-dependent bending loss. These integrated filters are capable of suppressing crosstalk and providing >15dB isolation over 40GHz, which is highly beneficial for terahertz-range wireless communications applications. We have used this diplexer in a simultaneous error-free wireless transmission of 300-GHz and 335-GHz channels at the aggregate data rate of 36Gbit/s.

Indoor free space optical (FSO) communication technology that provides high-speed connectivity to edge users is expected to be introduced in the near future mobile communication system, where the silicon photonics solid-state beam scanning device is a promising tool because of its low cost, long-term reliability, and other beneficial properties. However, the current two-dimensional beam scanning devices using grating coupler arrays have difficulty in increasing the transmission capacity because of bandwidth regulation. To solve the problem, we have introduced a broadband surface optical coupler, “elephant coupler,” which has great potential for combining wavelength and spatial division multiplexing technologies into the beam scanning device, as an alternative to grating couplers. The prototype port-selective silicon beam scanning device fabricated using a 300 mm CMOS pilot line achieved broadband optical beam emission with a 1 dB-loss bandwidth of 40 nm and demonstrated beam scanning using an imaging lens. The device has also exhibited free-space signal transmission of non-return-to-zero on-off-keying signals at 10 Gbps over a wide wavelength range of 60 nm. In this paper, we present an overview of the developed beam scanning device. Furthermore, the theoretical design guidelines for indoor mobile FSO communication are discussed.

The optical phased array (OPA) is an emerging non-mechanical device that enables high-speed beam steering by emitting precisely phase-controlled lightwaves from numerous optical antennas. In practice, however, it is challenging to drive all phase shifters on an OPA in a deterministic manner due to the inevitable fabrication-induced phase errors and crosstalk between the phase shifters. In this work, we fabricate a 16-element silicon photonic non-redundant OPA chip with integrated phase monitors and experimentally demonstrate accurate monitoring of the relative phases of light from each optical antenna. Under the beam steering condition, the optical phase retrieved from the on-chip phase monitors varies linearly with the steering angle, as theoretically expected.

We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

We have designed a near-infrared wavelength Si/CaF2 DFB quantum cascade laser and investigated the possibility of single-mode laser oscillation by analysis of the propagation mode, gain, scattering time of Si quantum well, and threshold current density. As the waveguide and resonator, a slab-type waveguide structure with a Si/CaF2 active layer sandwiched by SiO2 on a Si (111) substrate and a grating structure in an n-Si conducting layer were assumed. From the results of optical propagation mode analysis, by assuming a λ/4-shifted bragg waveguide structure, it was found that the single vertical and horizontal TM mode propagation is possible at the designed wavelength of 1.70µm. In addition, a design of the active layer is proposed and its current injection capability is roughly estimated to be 25.1kA/cm2, which is larger than required threshold current density of 1.4kA/cm2 calculated by combining analysis results of the scattering time, population inversion, gain of quantum cascade lasers, and coupling theory of a Bragg waveguide. The results strongly indicate the possibility of single-mode laser oscillation.

SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

This paper summarizes our recent studies on architecture, photonic integration, system validation and networking performance analysis of a flexible low-latency interconnect optical network switch (Flex-LIONS) for datacenter and high-performance computing (HPC) applications. Flex-LIONS leverages the all-to-all wavelength routing property in arrayed waveguide grating routers (AWGRs) combined with microring resonator (MRR)-based add/drop filtering and multi-wavelength spatial switching to enable topology and bandwidth reconfigurability to adapt the interconnection to different traffic profiles. By exploiting the multiple free spectral ranges of AWGRs, it is also possible to provide reconfiguration while maintaining minimum-diameter all-to-all interconnectivity. We report experimental results on the design, fabrication, and system testing of 8×8 silicon photonic (SiPh) Flex-LIONS chips demonstrating error-free all-to-all communication and reconfiguration exploiting different free spectral ranges (FSR0 and FSR1, respectively). After reconfiguration in FSR1, the bandwidth between the selected pair of nodes is increased from 50Gb/s to 125Gb/s while an all interconnectivity at 25Gb/s is maintained using FSR0. Finally, we investigate the use of Flex-LIONS in two different networking scenarios. First, networking simulations for a 256-node datacenter inter-rack communication scenario show the potential latency and energy benefits when using Flex-LIONS for optical reconfiguration based on different traffic profiles (a legacy fat-tree architecture is used for comparison). Second, we demonstrate the benefits of leveraging two FSRs in an 8-node 64-core computing system to provide reconfiguration for the hotspot nodes while maintaining minimum-diameter all-to-all interconnectivity.

Silicon photonics technology is a promising candidate for small form factor transceivers that can be used in data-center applications. This technology has a small footprint, a low fabrication cost, and good temperature immunity. However, its main challenge is due to the high baud rate operation for optical modulators with a low power consumption. This paper investigates an all-Silicon Mach-Zehnder modulator based on the lumped-electrode optical phase shifters. These phase shifters are driven by a complementary metal oxide semiconductor (CMOS) inverter driver to achieve a low power optical transmitter. This architecture improves the power efficiency because an electrical digital-to-analog converter (DAC) and a linear driver are not required. In addition, the current only flows at the time of data transition. For this purpose, we use a PIN-diode phase shifter. These phase shifters have a large capacitance so the driving voltage can be reduced while maintaining an optical phase shift. On the other hand, this study integrates a passive resistance-capacitance (RC) equalizer with a PIN-phase shifter to expand the electro-optic (EO) bandwidth of a modulator. Therefore, the modulation efficiency and the EO bandwidth can be optimized by designing the capacitor of the RC equalizer. This paper reviews the recent progress for the high-speed operation of an all-Si PIN-RC modulator. This study introduces a metal-insulator-metal (MIM) structure for a capacitor with a passive RC equalizer to obtain a wider EO bandwidth. As a result, this investigation achieves an EO bandwidth of 35.7-37 GHz and a 70 Gbaud NRZ operation is confirmed.

We review our research progress of multi-port optical switches based on the silicon photonics platform. Up to now, the maximum port-count is 32 input ports×32 output ports, in which transmissions of all paths were demonstrated. The switch topology is path-independent insertion-loss (PILOSS) which consists of an array of 2×2 element switches and intersections. The switch presented an average fiber-to-fiber insertion loss of 10.8 dB. Moreover, -20-dB crosstalk bandwidth of 14.2 nm was achieved with output-port-exchanged element switches, and an average polarization-dependent loss (PDL) of 3.2 dB was achieved with a non-duplicated polarization-diversity structure enabled by SiN overpass waveguides. In the 8×8 switch, we demonstrated wider than 100-nm bandwidth for less than -30-dB crosstalk with double Mach-Zehnder element switches, and less than 0.5 dB PDL with polarization diversity scheme which consisted of two switch matrices and fiber-type polarization beam splitters. Based on the switch performances described above, we discuss further improvement of switching performances.

A compact silicon photonic crystal waveguide (PCW) slow-light modulator is presented. The proposed modulator is capable of achieving a 64 Gbps bit-rate in a wide operating spectrum. The slow-light enhances the modulation efficiency in proportion to its group index ng. Two types of 200-µm-long PCW modulators are presented. These are low- and high-dispersion devices, which are implemented using a complementary metal-oxide-insulator process. The lattice-shifted PCW achieved low-dispersion slow-light and exhibited ng ≈ 20 with an operating spectrum Δλ ≈ 20 nm, in which the fluctuation of the extinction ratio is ±0.5 dB. The PCW device without the lattice shift exhibited high-dispersion, for which a large or small value of ng can be set on demand by changing the wavelength. It was found that for a large ng, the frequency response was degraded due to the electro-optic phase mismatch between the RF signals and slow-light even for such small-size modulators. Meander-line electrodes, which bypass and delay the RF signals to compensate for the phase mismatch, are proposed. A high cutoff frequency of 55 GHz was theoretically predicted, whereas the experimentally measured value was 38 GHz. A high-quality open eye pattern for a drive voltage of 1 V at 32 Gbps was observed. The clear eye pattern was maintained for 50-64 Gbps, although the drive voltage increased to 3.5-5.3 V. A preliminary operation of a 2-bits pulse amplitude modulation up to 100 Gbps was also attempted.

This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

We have developed the world's largest 16.7-inch hybrid in-cell touch panel. To realize the large sized in-cell touch panel, we applied a vertical Vcom system and low resistance sensor, which are JDI's original technologies. For glove touch function, we applied mutual bundled driving, which increases the signal intensity higher. The panel also has a low surface reflection, curved-shaped, and non-rectangular characteristics, which are particular requirements in the automotive market. The over 15-inch hybrid in-cell touch panel adheres to automotive quality requirements. We have also developed a force touch panel, which is a new human machine interface (HMI) based on a hybrid in-cell touch panel in automotive display. This study reports on the effect of the improvements on the in-plane variation of force touch and the value change of the force signal under different environment conditions. We also a introduce force touch implemented prototype.

With the advantages of higher blocking voltage, higher operation temperature, fast-switching characteristics, and lower switching losses, the silicon carbide (SiC) MOSFET has attracted more attentions and become an available replacement of traditional silicon (Si) power semiconductor in applications. Despite of all the merits above, electromagnetic interference (EMI) issues will be induced consequently by the ultra-fast switching transitions of the SiC MOSFET. To quickly and precisely assess the switching behaviors of the SiC MOSFET for EMI investigation, an analytical model is proposed. This model has comprehensively considered most of the key factors, including parasitic inductances, non-linearity of the junction capacitors, negative feedback effect of Ls and Cgd shared by the power and the gate stage loops, non-linearity of the trans-conductance, and skin effect during voltage and current ringing stages, which will considerably affect the switching performance of the SiC MOSFET. Additionally, a finite-state machine (FSM) is especially utilized so as to analytically and intuitively describe the switching behaviors of the SiC MOSFET via Stateflow. Based on double pulse test (DPT), the effectiveness and correctness of the proposed model are validated through the comparison between the calculated and the measured waveforms during switching transitions. Besides, the model can appropriately depict the spectrum of the drain-source voltage of the MOSFET and is suitable for EMI investigation in applying of SiC devices.