In this paper, we present a design method for fixed-width squarer that receives an n-bit input and produces an n-bit squared product. To efficiently compensate for the truncation error, modified Booth-folding encoder signals are used for the generation of error compensation bias. The truncated bits are divided into two groups (major and minor) depending upon their effects on the truncation error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the proposed fixed-width squarers have lower error than other fixed-width squarers and are cost-effective.

High power consumption and slow access of enlarged and multiported register files make it difficult to design high performance superscalar processors. The clustered architecture, where the conventional monolithic register file is partitioned into several smaller register files, is expect to overcome the register file issues. In the clustered architecture, the more a monolithic register file is partitioned, the lower power and faster access register files can be realized. However, the partitioning causes losses of IPC (instructions per clock cycle) due to communication among register files. Therefore, degree of partitioning has a strong impact on the trade-off between power consumption and performance. In addition, the organization of partitioned register files also affects the trade-off. In this paper, we attempt to investigate appropriate degrees of partitioning and organizations of partitioned register files in a clustered architecture to assess the trade-off. From the results of execute-driven simulation, we find that the organization of register files and the degree of partitioning have a strong impact on the IPC, and the configuration with non-consistent register files can make use of the partitioned resources more effectively. From the results of register file access time and energy modeling, we find that the configurations with the highly partitioned non-consistent register file organization can receive benefit of the partitioning in terms of operating frequency and access energy of register files. Further, we examine relationship between IPS (instructions per second) and the product of IPC and operating frequency of register files. The results suggest that highly partitioned non-consistent configurations tends to gain more advantage in performance and power.

Cache performance optimization is an important design consideration in building high-performance embedded processors. Unlike general-purpose microprocessors, embedded processors can take advantages of application-specific information in optimizing the cache performance. One of such examples is to use modified cache index bits (over conventional index bits) based on memory access traces from key target embedded applications so that the number of conflict misses can be reduced. In this paper, we present a novel fine-grained cache reconfiguration technique which allows an intra-program reconfiguration of cache index bits, thus better reflecting the changing characteristics of a program execution. The proposed technique, called dynamic reconfiguration of index bits (DRIB), dynamically changes cache index bits in the function level. This compiler-directed and fine-grained approach allows each function to be executed using its own optimal index bits with no additional hardware support. In order to avoid potential performance degradation by frequent cache invalidations from reconfiguring cache index bits, we describe an efficient algorithm for selecting target functions whose cache index bits are reconfigured. Our algorithm ensures that the number of cache misses reduced by DRIB outnumbers the number of cache misses increased from cache invalidations. We also propose a new cache architecture, Two-Level Indexing (TLI) cache, which further reduces the number of conflict misses by intelligently dividing indexing steps into two stages. Our experimental results show that the DRIP approach combined with the TLI cache reduces the number of cache misses by 35% over the conventional cache indexing technique.

Tailoring industrial standards is done to reduce costs and improve quality for a particular project. This paper proposes using Bayesian Belief Network (BBN) analysis to support tailoring decision-making under uncertainties. However, there are two major problems associated with the objectivity of BBNs; that is, the construction of the causal inference diagrams and the assignment of probabilities of their dependency relations. We have developed a method to solve the first problem. In general, the relations among different activities, resources, and products addressed in software standards can be expressed more directly in Unified Modeling Language (UML) diagrams than in BBN's. Such relations include association, aggregation, or inheritance relations. We have developed a schema to construct BBNs for process tailoring from given UML diagrams that model a particular standard. The proposed approach systematically constructing BBNs can also be used to assist decision-making in other software project management activities, such as planning and risk management.

Privacy is increasingly viewed as a key concern in multi-agent based algorithms for Distributed Constraint Satisfaction Problems (DCSP) such as the Meeting Scheduling (MS) problem. Many algorithms aim for a global objective function and as a result, incur performance penalties in computational complexity and personal privacy. This paper describes a mobile agent-based scheduling scheme called Efficient and Privacy-aware Meeting Scheduling (EPMS), which results in a tradeoff among complexity, privacy, and global utility. It also introduces a privacy loss model for collaborative computation, multiple criteria for evaluating privacy in the MS problem, and a privacy measurement metric called the Min privacy metric. We have utilized a common computational space in EPMS for reducing the complexity and the privacy loss in the MS problem. The analytical results show that EPMS has a polynomial time computational complexity. In addition, simulation results show that the obtained global utility for scheduling multiple meetings with EPMS is close to the optimal level and the resulting privacy loss is less than for those in existing algorithms.

Due to the exponentially increasing threat of cyber attacks, many e-commerce organizations around the world have begun to recognize the importance of information security. When considering the importance of security in e-commerce, we need to train e-commerce security experts who can help ensure the reliable deployment of e-commerce. The purpose of this research is to design and evaluate an e-commerce security curriculum useful in training e-commerce security experts. In this paper, we use a phase of the Delphi method and the Analytic Hierarchy Process (AHP) method. To validate our results, we divide the respondents into two groups and compare the survey results.

We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.

This letter proposes a broadcast scheme for use in ad hoc networks using variable-range transmission power. Preserving energy and ensuring a high delivery ratio of broadcast packets are crucial tasks for broadcasting in ad hoc networks. Using individual broadcast relaying nodes to dynamically vary the transmission range can help saving power and reduce interference during communication. We analyzed the performance of the proposed scheme and compared it to other prevalent broadcast schemes for wireless ad hoc networks based on common-range transmission power.

A method to detect open node defects that cannot be detected by the conventional IDDQ test method has previously been proposed employing a sinusoidal wave superposed on the DC supply voltage. The present paper proposes a strategy to improve the detectability of the test method by means of frequency analysis of the supply current. In this strategy, defects are detected by determining whether secondary harmonics of the sinusoidal wave exist in the supply current. The effectiveness of the method is confirmed by experiments on two CMOS NAND gate packages (SSIs).

Web metering is an effective means of measuring the number of visits from clients to Web servers during a specific time frame. Naor and Pinkas, in 1998, first introduced metering schemes to evaluate the popularity of Web servers. Ogata and Kurosawa proposed two schemes that improve on the Naor-Pinkas metering schemes. This study presents a Web metering scheme which is based on the bilinear pairings and built on the GDH group. The proposed scheme can resist fraud attempts by malicious Web servers and disruptive attacks by malicious clients.

This paper describes the explicit modeling of a state duration's probability density function in HMM-based speech synthesis. We redefine, in a statistically correct manner, the probability of staying in a state for a time interval used to obtain the state duration PDF and demonstrate improvements in the duration of synthesized speech.

In the case of miniaturized telemetry capsules, such as a capsule endoscope that can acquire and transmit images from the intestines, the size and the power consumption of the module are restricted. In the capsule endoscopes, it is desirable that the control function can capacitate the sampling of digestive fluid and tissue, drug delivery, and locomotion. In this paper, the control function was embodied by bi-directional communication. A CPLD (complex programmable logic device) controller was designed and implemented for the bi-directional communication in capsule endoscope. The diameter of capsule was 12 mm and the length was 30 mm. The performance of implemented capsule was verified by in-vivo animal experiments.