Recent advanced technology makes digital circuits small and the number of digital functional blocks that can be integrated on a single chip is increasing rapidly. On the other hand, reduction in the size of analog circuits has been insufficient. This means that the analog circuit area is relatively large, and reducing analog circuit area can be effective to make a low cost radio receiver. In this paper, a new wireless receiver architecture that occupies small analog area is proposed, and measured results of the core analog blocks are described. To reduce the analog area, a balanced 3-phase analog system is adopted and the functions of analog baseband filters and VGAs are moved to the digital domain. The test chip consists of a 3-phase downconverter and a 3-phase ADC. There is no analog baseband filter on the chip and the analog filter is assumed to be replaced with a digital filter. The downconverter and ADC occupy 0.28 mm2. The measured results show the possibility that the requirements for IMT-2000 are fulfilled even with a small chip area.

A 2 to 5 GHz-band self frequency dividing quadrature mixer utilizing current re-use configuration with small size and broad band operation is proposed for a direct conversion receiver and a low-IF receiver of cognitive radio. The proposed mixer operates at twice the LO frequency by directly using a static type flip-flop frequency divider as the LO switching circuit for quadrature signal generation. The current re-use configuration is realized because the dc current of the frequency divider and the RF common-emitter amplifier share the same current flow path. Simulations and experiments verify that the proposed mixer offers broad band operation, miniaturization, and low power consumption. The mixer IC fabricated by 0.35 µm SiGe-BiCMOS technology achieved the conversion gain of 20.6 dB, noise figure of 11.9 dB and EVM for π/4-shift QPSK signal of 4.4% at 2.1 GHz with power consumption of 15 mW and size of 0.22 0.31 mm2. For the confirmation of broad band operation, the characteristics of conversion gain and noise figure were measured at 5.2 GHz. The proposed mixer could operate at 5.2 GHz with enough conversion gain, but the noise figure was inferior to that of 2.1 GHz. Therefore the further investigation and improvement about the noise figure will be needed for higher frequency.

This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

An even harmonic quadrature mixer (EH-QMIX) with a balanced configuration is proposed for a direct conversion receiver. The unit even harmonic mixer (EHMIX) used for I/Q paths consists of two anti parallel diode pairs (APDPs) and a pair of diplexers. When the second harmonic of LO (2LO) from the LO section is applied to the LO port as a spurious component, a conventional single-ended EHMIX using APDP converts the 2LO leakage from the LO section into the baseband and the d.c. offset and the self-detected LO noise arise at the baseband degrade the sensitivity. This proposed balanced EHMIX configuration can cancel out the 2LO leakage in itself. Therefore, the d.c. offset and the LO noise are significantly suppressed and the degradation of the sensitivity can be avoided. The suppression characteristic of the d.c. offset and the LO noise are verified by the simulation and the measurements. By using this balanced configuration, the fabricated EH-QMIX achieves wider frequency band characteristic than that of the single-ended EH-QMIX, and it shows 20% relative bandwidth at L-band.

This paper presents an even harmonic quadrature mixer (EH-QMIX) with a simple filter configuration and an integrated LTCC module including LNAs, band rejection filters (BRFs), and the proposed EH-QMIX for W-CDMA direct conversion receiver (DCR). Since the DCR has no spurious responses, a BRF instead of a high-Q band pass filter can be applicable for eliminating undesired signals and it can be built in the LTCC substrates easily. As LO frequency is half of RF frequency in the EH-QMIX, diplexer can be composed of simple filters and it can be also integrated in the substrates. As a result, the whole RF circuits of the EH-DCR using a proposed EH-QMIX are integrated in the LTCC module and miniaturization of the receiver is achieved. Moreover, in order to suppress the degradation of the amplitude and the phase imbalances in the quadrature mixer caused by interferences of signals, RF characteristics of the circuits in the mixer such as reflection coefficients, isolations are discussed. A developed LTCC module shows good performances for W-CDMA direct conversion receiver.

An RF front-end using a six-port circuit is a promising technology for realization of a compact software defined radio (SDR) receiver. Such a receiver, called a six-port direct conversion receiver (DCR), consists of analog circuit and digital signal processing components. The six-port DCR itself outputs four different linear combinations of received and local signals. The output powers are measured at each port, and the received signal is recovered by solving a set of linear equations. This receiver can easily cover a wide frequency band unlike the conventional DCR since it does not require the precise orthogonality that the conventional one does. In this paper, we propose a novel calibration method for a six-port system that includes nonlinear circuits such as diode detectors. We demonstrated the demodulation performance of a six-port DCR by computer simulation and experiments at 1.9, 2.45, and 5.85 GHz.

A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.