Realizing frequency rectangular characteristics using a planar circuit made of a normal conductor material such as a printed circuit board (PCB) is difficult. The reason is that the corners of the frequency response are rounded by the effect of the low unloaded quality factors of the resonators. Rectangular frequency characteristics are generally realized by a low-noise amplifier (LNA) with flat gain characteristics and a high-order bandpass filter (BPF) with resonators having high unloaded quality factors. Here, we use an LNA and a fourth-order flat passband BPF made of a PCB to realize the desired characteristics. We first calculate the signal and noise powers to confirm any effects from insertion loss caused by the BPF. Next, we explain the design and fabrication of an LNA, since no proper LNAs have been developed for this research. Finally, the rectangular frequency characteristics are shown by a circuit combining the fabricated LNA and the fabricated flat passband BPF. We show that rectangular frequency characteristics can be realized using a flat passband BPF technique.

Matching circuits using LC elements are widely applied to high-frequency circuits such as power amplifier (PA) and low-noise amplifier (LNA). For determining matching condition of multi-stage matching circuits, this paper shows that any multi-stage LC-Ladder matching circuit with resistive termination can be decomposed to the extended L-type matching circuits with resistive termination containing negative elements where the analytical solution exists. The matching conditions of each extended L-type matching circuit are obtained easily from the termination resistances and the design frequency. By synthesizing these simple analysis solutions, it is possible to systematically determine the solution even in a large number of stages (high order) matching circuits.

This paper presents on-wafer noise figure (NF) de-embedding method of differential low noise amplifier (LNA). The characterization of NF was set up and referred as multi-stage network. The Friis law was applied to improve from the noise contributions from the subsequent stages. The correlated differential NF is accurately obtained after de-embedding the noise contribution from the interconnections and external components. Details of equations and measurement procedure are reported in this work. A 2.4GHz differential LNA was tested to demonstrate the feasibility of measurement and showed precise NF compared with other methods. The result shows an NF of 0.57dB achieved using de-embedding method and 1.06dB obtained without the de-embedding method. This is an improvement of 0.49dB of NF measurement.

We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.

An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing between the interfering signals in the two-tone test of DTV tuners. Fabricated in a 0.18 µm CMOS technology, the LNA core size is 0.21 mm2. Measurements show that the LNA IIP3 and IIP2 are +12 dBm and +21 dBm, respectively. The IIP3 variation is less than 5 dB in the 10 MHz to 200 MHz frequency spacing range. A voltage gain of 14.5 dB and a noise figure below 4 dB are achieved in a frequency range from 100 MHz to 1 GHz. The LNA consumes 11 mA from a 1.8 V supply voltage.

The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13 µm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT. The measured gain was 18.6 dB with VDD = 1.2 V and increased up to 20.2 dB with VDD = 1.8 V at 66 GHz. The measured NF showed a minimum value of 7.0 dB at 62 GHz. DC power consumption was 24 mW with VDD = 1.2 V. The size of the fabricated circuit is as compact as 0.45 mm 0.69 mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6 dB and average NF degradation of 1.3 dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills.

A resistive feedback-based inductive source degeneration ultra-wideband (UWB) CMOS low noise amplifier (LNA) with floating n-well terminals has been proposed. The resistive feedback technique provides wideband input matching with a small amount of noise degradation by reducing the quality factor of the input resonant circuit. In addition, all n-wells terminals of the triple-well RF transistors are connected to the supply voltage through high value resistors in order to reduce unwanted parasitic capacitances, leading to improvement of the RF performance of the proposed LNA. The proposed UWB LNA is implemented in 0.13 µm CMOS technology and all inductors are fully integrated in this work. Measurement results show a power gain of 10 dB from 3 GHz to 6 GHz, a minimum (maximum) noise figure of 2.3 dB (3.8 dB), an input return loss of better than -8 dB, and an input referred IP3 of -7 dBm. The fabricated chip consumes only 5 mA from a 1.5 V supply voltage.

In this paper, we present the development of an advanced MMIC receiver for a 94-GHz band passive millimeter-wave (PMMW) imager. Our configuration is based on a Dicke receiver in order to reduce fluctuations in the detected voltage. By introducing an electronic switch in the MMIC, we achieved a high resolution millimeter-wave image in a shorter image collection time compared to that with a conventional mechanical chopper. We also developed an imaging array using MMIC receivers.

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65 nm and 130 nm CMOS technologies, respectively.

A CMOS low noise amplifier (LNA) for low-power ultra-wideband (UWB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonant frequencies. This work is implemented in 0.18-µm CMOS process and shows a 2.4-9.4-GHz bandwidth. The amplifier provides a maximum forward gain (S21) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 4.1 dB and an IIP3 of -3.5 dBm have been demonstrated.

In the design of cascode CMOS low-noise amplifiers, the gate-drain capacitance is generally neglected because it is thought to be small enough compared to gate-source capacitance. However, a careful examination will reveal the fact that the drain impedance of the input transistor significantly affects the input impedance through the gate-drain capacitance, especially as the CMOS technology getting more and more advanced. Moreover, the substrate coupling network of the input transistor also comes into play when the drain impedance of the input transistor is high enough compared to the substrate coupling network. In order to make input matching easier, it is desirable to know the details of the substrate coupling network. Unfortunately, designers generally do not have enough information about the technology they have used, not to mention knowing the details concerning the substrate coupling network. As a matter of fact, designers generally do have foundry provided component models that contain information about the substrate coupling network. This gives us the chance to minimize its effect and predict the input impedance of a low noise amplifier more accurately. In this paper, we show that the effect of the substrate coupling network can be ignored by keeping the drain impedance of the input transistor low enough and a proper drain impedance can then be chosen to achieve input matching without the need of iteration steps. Simulation results of a 2.4 GHz CMOS low noise amplifier using foundry provided component models are also presented to demonstrate the validation of the proposed input matching method.

A fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a down conversion mixer, a digitally programmable gain amplifier, an on-chip VCO, and a fractional-N frequency synthesizer is designed using a 0.35-µm CMOS process. A multi-stage ring shaped on-chip LC-VCO exhibiting bandpass characteristics overcomes the limitation of low-Q components in the tank circuits and improves the phase noise performance. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2 mm2 die area with minimal external components.

We present ultra low noise- and wide dynamic range performances of an AlGaN/GaN heterostructure FET (HFET). An HFET fabricated on a high quality epitaxial layers grown on a semi-insulating SiC substrate exhibited impressively low minimum noise figure (NF min ) of 0.4 dB with 16 dB associated gain at 2 GHz. The low NF (near NF min ) operation was possible in a wide drain bias voltage range, i.e. from 3 V to 15 V. At the same time, the device showed low distortion character as indicated by the high third order input intercept point (IIP3), +13 dBm. The excellent characteristics are attributed to three major factors: (1) high quality epitaxial layers that realized a high transconductance and very low buffer leakage current; (2) excellent device isolation made by selective thermal oxidation; (3) ultra low gate leakage current realized by Pd based gate. The results demonstrate that the AlGaN/GaN HFET is a strong candidate for front-end LNAs in various mobile communication systems where both the low noise and the wide dynamic range are required.

A three-mode switched-LNA has been developed using a 0.25 µm SiGe BiCMOS technology. The LNA features low noise figure (NF) performance, while achieving both low dissipation power and low distortion characteristics. The proposed MOSFET switch incorporating a newly developed switch circuit with a triple-well structure, which changes the LNA's mode, provides a parasitic capacitance of just 0.52 times that of a conventional MOSFET switch. This results in a significant NF improvement, by 0.16-0.33 dB, for the three-mode switched-LNA compared to a conventional LNA. Extensive studies of the MOSFET switch with regard to the structural parameters and the doping profiles are reported. Experimental results and the overall performance of a trial IC incorporating the three-mode switched-LNA are also given.

As an RF high Tc superconducting (HTS) front end for a microwave receiver, we propose a new design method for the broadband matching circuit composed of coplanar waveguide (CPW) meanderline resonators connecting a slot antenna with CMOS low noise amplifier (LNA). The parameters of the antenna sections with matching circuit are calculated and simulated with the circuit simulator and electromagnetic field simulator. CMOS LNA was designed and its input and output impedances and noise figure were obtained by SPICE simulation.

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

An ultra low-noise and highly selective, experimental 2-GHz band cryogenic receiver front end (CRFE) has been newly developed for cellular base stations. It utilizes a high-Q superconducting filter, a very low noise cryogenic amplifier, and a highly reliable cooler that is very compact. Fundamental design of the CRFE is investigated. First, the equivalent noise temperature of the CRFE and the effect of improving CRFE sensitivity on base station reception are discussed. Next, essential technologies and fundamental characteristics of each component are described. Finally, influence of antenna noise, such as ground noise and man-made noise, is estimated through field tests both in urban and suburban areas.