This paper presents a novel wide tuning range CMOS Voltage Controlled Oscillator (VCO). VCO uses an on-chip variable inductor as an additional variable element to extend the tuning range of VCO. The fabricated variable inductor achieves the variable range of 35%. The VCO was fabricated using 0.35 µm standard CMOS process, and can be tuned continuously from 2.13 GHz to 3.28 GHz (tuning range of 38%) without degradation of phase noise. Wide tunable LC-VCO using a variable inductor is one of the key circuits for reconfigurable RF circuit.

This paper proposes a novel wide-tunable CMOS low-noise amplifier (LNA) using a variable inductor. The variable inductance can be tuned by shielding the magnetic flux, which uses a metal plate above the inductor. The metal plate can be moved using a MEMS actuator. At the present time, the MEMS actuator has not been implemented yet. In this paper, we present a feasibility study on the proposed LNA using the variable inductor. The proposed LNA uses two variable inductors for input and output impedance matching-tuning. The LNA achieves a power gain (PG) of over 10 dB at a tuning range of 1.6-3.2 GHz.

The roadside network system for ITS services uses microcells in its access infrastructure. For the roadside network that provides the uninterrupted communication using microcells such as DSRC, an effective communication control scheme must be established so as to manage the communication passes to vehicles in the network. One of the fundamental requirements for the communication control scheme for the roadside network is to assure fault-tolerance, which means in this system that the communication control mechanism needs to be managed even in part of the base stations in the network might be in fault. On the other hand, for the communication control in the roadside network using microcells, issues to be solved are the handover mechanism for taking over connection information to provide uninterrupted communication environment, which causes the degradation of the end-to-end throughput. In order to solve those problems, the authors developed a communication control scheme. We implemented the scheme as the specific 'ADS algorism' to control the communication zone dynamically, which works effectively on the Autonomous Decentralized System (ADS) communication platform. Furthermore, we also developed the specific ADS algorism to assure fault-tolerance for the communication zone control, which can reconfigure the communication zone in case the BSs in the roadside network are in fault and can keep the operations by the reconfigured communication zone. We evaluated the ADS algorism for the communication zone control by computer simulation. The results show the effectiveness of the ADS algorism for the dynamic communication zone control mechanism and for the fault-tolerant mechanism for communication zone reconfiguration on fault.

A multi-port device is characterized using measurement results of a two-port Vector Network Analyzer (VNA) with four different structures. The loads used as terminations are open-, or short-circuited transmission lines (TLs), which are characterized along with Ground-Signal-Ground pads based on L-2L de-embedding method. A new characterization method for a four-port device is introduced along with its theory. The method is validated using simulation and measurement results. The characterized four-port device is a Crossing Transmission Line (CTL), mainly used for over-pass or under-pass of RF signals. Four measurement results are used to characterize the CTL. The S-parameter response of the CTL is found. To compare the results, reconstructed responses compared with the measurements. Results show good agreement between the measured and modeled results from 1 GHz to 110 GHz.

Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. The input-referred jitter is lowered by using a successive-approximated-register analog-to-digital converter (SAR-ADC)-based sampling phase detector (SPD). A stacked reference buffer is introduced to reduce the transient short-circuit current for low power and low reference spur. The locking issue due to the steady-state phase error in a type-I PLL and the limited range of the phase detector is addressed using a TDC-assisted loop. The loop stability and phase noise are analyzed, suggesting a trade-off for the minimum jitter. The solutions in detail are described. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.0 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm2 area, with 50 MHz reference frequency and 2.0 GHz output frequency.

Currently, multi-party video conference does not provide equivalent quality in comparison to face-to-face conference. One assumed reason is that participants cannot be aware of "who is focusing on whom". We introduce virtual space to a multi-party conference system, allocating avatars in a space. We also introduce intuitive input interface using motion processor in order to construct a multi-party conference system, which the user can use without being aware of it. A new displaying method is essential for this system, and we introduce a way by which a user can obtain the feedback of which user he/she is focusing on. We introduce e-MulCS as the system that fulfils these proposals. By comparing this system with the video conference system, the results show that our system supports the intuitive multi-party communication better.

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.

This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total isolation becomes less than -50 dB with more than 0.4 mm PA-to-LNA distance.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.

This paper presents a methodology for optimizing the layout of on-chip spiral inductors using structural parameters and design frequency in a response surface method. The proposed method uses scattering parameters (S-parameter) to express inductor characteristics, and hence is independent of spiral geometries and equivalent circuit models. The procedure of inductor optimization is described, and a design example is presented.

The equivalent anisotropic material parameters of metal dummy fills in a CMOS chip were extracted through an eigenmode analysis of a unit-cell of a space filled with metal dummies. The validity of the parameters was confirmed by comparing the S-parameters of a parallel-plate waveguide with the metal dummy fills and their effective material properties. The validity of the effective material properties was also confirmed by using them in a simulation of an on-chip dipole antenna.

This paper investigates a clock frequency generator for ultra-low-voltage sub-picosecond-jitter clock generation in future 0.5-V LSI and power aware LSI. To address the potential possible solution for ultra-low-voltage applications, a 0.5 V clock frequency generator is proposed and implemented. Significant performances, in terms of sub 1-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub 1-mW PDC, demonstrated the viable replacement of ring oscillators in low-voltage and low-jitter clock generator.

The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0 dBc/Hz of FoM, can be extended from 6.5-12.5 GHz to 1.5-12.5 GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. A consideration of the baseband carrier recovery circuit helps estimate phase noise requirement for high modulation scheme. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing PD noise resulting in low in-band phase noise while sampling loop filter helps reduce spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively. It consumes only a total power of 33mW. The jitter-power figure-of-merit (FOM) is -231dB which is the highest among the state of the art >20GHz fractional-N PLLs using a low reference clock (<200MHz). The measured reference spurs are less than -80dBc.

This paper presents a multi-band WCDMA receiver consisting of a multi-band low noise amplifier (LNA), a multi-band mixer and an inter-stage tunable notch filter. The notch filter is used to suppress Tx leakage, and 0.8–1.5 GHz (66%) of tuning range is achieved. The receiver achieves 33 and 30 dB conversion gain, 6.4 and 8 dB NF, 50 and 35.5 dBm IIP2, and -6 and -4.7 dBm IIP3 at 0.8 and 1.5 GHz, respectively. The power consumption is 121 mW from a 1.8-V power supply. The receiver is implemented in a 0.18-µm CMOS process.

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4,GHz WiFi, and 60,GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such as the shift from digitally-assisted analog circuit to digitally-designed analog circuit will also be discussed.