Signal processing using delta-sigma modulated bit streams is reviewed, along with related topics in stochastic computing (SC). The basic signal processing circuits, adders and multipliers, are covered. In particular, the possibility of preserving the noise-shaping properties inherent in delta-sigma modulation during these operations is discussed. Finally, the root mean square error for addition and multiplication is evaluated, and the performance improvement of signal processing in the delta-sigma domain compared with SC is verified.

Self-dithered digital delta-sigma modulators (DDSMs) are commonly used in fractional-N frequency synthesizers due to their ability to eliminate unwanted spurs from the synthesizer’s spectra without requiring additional hardware. However, when operating with a low-bit input, self-dithered DDSMs can still suffer from spurious tones at certain inputs. In this paper, we propose a self-dithered MASH 1-1-1-1 structure to mitigate the spur issue in the self-dithered MASH DDSMs. The proposed self-dithered MASH 1-1-1-1 suppresses the spurs with shaped dithering and achieves 4th order noise shaping.

A feedforward (FF) network using ΔΣ modulators is investigated to implement a non-binary analog-to-digital (A/D) converter. Weighting coefficients in the network are determined to suppress the generation of quantization noise. A moving average is adopted to prevent the analog signal amplitude from increasing beyond the allowable input range of the modulators. The noise transfer function is derived and used to estimate the signal-to-noise ratio (SNR). The FF network output is a non-uniformly distributed multi-level signal, which results in a better SNR than a uniformly distributed one. Also, the effect of the characteristic mismatch in analog components on the SNR is analyzed. Our behavioral simulations show that the SNR is improved by more than 30 dB, or equivalently a bit resolution of 5 bits, compared with a conventional first-order ΔΣ modulator.

In this paper, we propose a direct digital RF transmitter with a 1-bit band-pass delta-sigma modulator (BP-DSM) that uses high order image components of the 7th Nyquist zone in Manchester coding for microwave and milimeter wave application. Compared to the conventional non-return-to-zero (NRZ) coding, in which the high order image components of 1-bit BP-DSM attenuate severely in the form of sinc function, the proposed 1-bit direct digital RF transmitter in Manchester code can improve the output power and signal-to-noise ratio (SNR) of the image components at specific (4n-1)th and (4n-2)th Nyquist Zone, which is confirmed by calculating of the power spectral density. Measurements are made to compare three types of 1-bit digital-to-analog converter (DAC) signal in output power and SNR; NRZ, 50% duty return-to-zero (RZ) and Manchester coding. By using 1 Vpp/8Gbps DAC output, 1-bit signals in Manchester coding show the highest output power of -20.3dBm and SNR of 40.3dB at 7th Nyquist Zone (26GHz) in CW condition. As a result, compared to NRZ and RZ coding, at 7th Nyquist zone, the output power is improved by 8.1dB and 6dB, respectively. Meanwhile, the SNR is improved by 7.6dB and 4.9dB, respectively. In 5Mbps-QPSK condition, 1-bit signals in Manchester code show the lowest error vector magnitude (EVM) of 2.4% and the highest adjacent channel leakage ratio (ACLR) of 38.2dB with the highest output power of -18.5dBm at 7th Nyquist Zone (26GHz), respectively, compared to the NRZ and 50% duty RZ coding. The measurement and simulation results of the image component of 1-bit signals at 7th Nyquist Zone (26GHz) are consistent with the calculation results.

This paper presents a novel delta-sigma modulator that uses a switched-capacitor (SC) integrator with the structure of a finite impulse response (FIR) filter in a loop filter configuration. The delta-sigma analog-to-digital converter (ΔΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. Increasing the gain coefficient of the integrator in the loop filter configuration of the ΔΣADC suppresses the quantization noise that occurs in the signal band. However, there is a trade-off relationship between the integrator gain coefficient and system stability. The SC integrator, which contains an FIR filter, can suppress quantization noise in the signal band without requiring an additional operational amplifier. Additionally, it can realize a higher signal-to-quantization noise ratio. In addition, the poles that are added by the FIR filter structure can improve the system's stability. It is also possible to improve the flexibility of the pole placement in the system. Therefore, a noise transfer function that does not contain a large gain peak is realized. This results in a stable system operation. This paper presents the essential design aspects of a ΔΣADC with an FIR filter. Two types of simulation results are examined for the proposed first- and second-order, and these results confirm the effectiveness of the proposed architecture.

The 1-bit digital radio frequency (DRF) transmitter using a band-pass delta-sigma modulator (BP-DSM) can output a radio frequency (RF) signal carrying a binary data stream with a constant data rate regardless of the carrier frequency, which makes it possible to transmit RF signals over digital optical links with a constant bit rate. However, the optical link requires a line coding, such as 8B10B or 64B66B, to constrain runlength and disparity, and the line coding corrupts the DRF power spectrum owing to additional or encoded data. This paper proposes a new line coding for BP-DSM, which is able to control the runlength and the disparity of the 1-bit data stream by adding a notch filter to the BP-DSM that suppresses the low frequency components. The notch filter stimulates the data change and balances the direct current (DC) components. It is demonstrated that the proposed line coding shortens the runlength from 50 bits to less than 8 bits and reduces the disparity from several thousand bits to 5 bits when the 1-bit DRF transmitter outputs an LTE signal with 5 MHz bandwidth, when using carrier frequencies from 0.5GHz to 2GHz and an output power variation of 60dB.

This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using column-parallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using column-parallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise)2(power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS' performance in all the pixel rates. Using the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified.

The 1-bit band-pass delta-sigma modulator (BP-DSM) achieves high resolution if it uses an oversampling technique. This method can generate concurrent dual-band RF signals from a digitally modulated signal using a 1-bit digital pulse train. It was previously reported that the adjacent channel leakage ratio (ACLR) deteriorates owing to the asymmetrical waveform created by the pulse transition mismatch error of the rising and falling waveforms in the time domain and that the ACLR can be improved by distortion compensation. However, the reported distortion compensation method can only be performed for single-band transmission, and it fails to support multi-band transmission because the asymmetrical waveform compensated signal extends over a wide frequency range and is itself a harmful distortion outside the target band. Unfortunately, the increase of out-of-band power causes the BP-DSM unstable. We therefore propose a distortion compensator for a concurrent dual-band 1-bit BP-DSM that consists of a noise transfer function with a quasi-elliptic filter that can control the out-of-band gain frequency response against out-of-band oscillation. We demonstrate that dual-band LTE signals, each with 40MHz (2×20MHz) bandwidth, at 1.5 and 3.0GHz, can be compensated concurrently for spurious distortion under various combinations of rising and falling times and ACLR of up to 48dB, each with 120MHz bandwidth, including the double sided adjacent channels and next adjacent channels, is achieved.

This work develops a third-order multibit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18µm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

We propose an architecture for a 1-bit band-pass delta-sigma modulator (BP-DSM) that outputs concurrent multiband RF signals. The proposed BP-DSM consists of parallel bandpass filters (BPFs) in the feedback loop to suppress the quantization noise at each target frequency band while maintaining the stability. Each BPF is based on second-order parallel infinite impulse response (IIR) filters. This architecture can unify and reconfigure the split BPFs according to the number of bands. The architecture complexity is proportional to the bandwidth of each RF signal and is independent of the carrier spacing between the bands. The conventional architecture of a concurrent multiband digital modulator, reported previously, has multiple input ports to the dedicated BPF at each band and so it cannot be efficiently integrated. Measurements show that the proposed architecture is feasible for transmitting a concurrent dual-band and a triple-band by changing the 1-bit digital data stream while keeping a data transmission rate of 10Gb/s. We demonstrate that the proposed architecture outputs the signal with LTE intra-band and inter-band carrier aggregation on 0.8GHz, 2.1GHz and 3.5GHz, each with 40MHz bandwidth in 120MHz aggregated bandwidth, whose bandwidth surpasses the bandwidth with carrier aggregation of LTE-A up to 100MHz. Adjacent channel leakage ratios of -49dBc and -46dBc are achieved at 3.5GHz in the concurrent dual-band and triple-band, respectively.

This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fsrms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

This paper proposes 1-bit feedforward distortion compensation for digital radio frequency conversion (DRFC) with 1-bit bandpass delta-sigma modulation (BP-DSM). The 1-bit BP-DSM allows direct RF signal transmission from a digitally modulated signal. However, it has been previously reported that 1-bit digital pulse trains with non-ideal rectangle waveform cause spectrum regrowth. The proposed architecture adds a feedforward path with another 1-bit BP-DSM and so can cancel out the distortion components at any target carrier frequency. Both the main signal and the distortion compensation signal are 1-bit digital pulse trains and so no additional analog RF circuit is required for distortion compensation. Simulation results show that the proposed method holds the adjacent channel leakage ratio to 60dB for LTE signal transmission. A prototype of the proposed 1-bit DRFC with an additional 1-bit BP-DSM in the feedforward path shows an ACLR of 50dB, 4dB higher than that of the conventional 1-bit DRFC.

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm2 and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

A novel delta-sigma modulator that employs a non-uniform quantizer whose spacing is adjusted by reference to the statistical properties of the input signal is proposed. The proposed delta-sigma modulator has less quantization noise compared to the one that uses a uniform quantizer with the same number of output values. With respect to the quantizer on its own, Lloyd proposed a non-uniform quantizer that is best for minimizing the average quantization noise power. The applicable condition of the method is that the statistical properties of the input signal, the probability density, are given. However, the procedure cannot be directly applied to the quantizer in the delta-sigma modulator because it jeopardizes the modulator's stability. In this paper, a procedure is proposed that determine the spacing of the quantizer with avoiding instability. Simulation results show that the proposed method reduces quantization noise by up to 3.8 dB and 2.8 dB with the input signal having a PAPR of 16 dB and 12 dB, respectively, compared to the one employing a uniform quantizer. Two alternative types of probability density function (PDF) are used in the proposed method for the calculation of the output values. One is the PDF of the input signal to the delta-sigma modulator and the other is an approximated PDF of the input signal to the quantizer inside the delta-sigma modulator. Both approaches are evaluated to find that the latter gives lower quantization noise.

This paper considers a simple type of Dynamic Element Matching (DEM), Clocked Averaging (CLA) method referred to as one-element-shifting (OES) and its effectiveness for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique discussed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the other published DEM methods. With this OES, a 3rd order, 10 MHz bandwidth continuous-time DSM is implemented in 90 nm CMOS process. The measured SFDR attains 83 dB for a 10 MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10 dB.

This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.