This study proposes a low-complexity permittivity estimation for ground penetrating radar applications based on a contrast source inversion (CSI) approach, assuming multilayered ground media. The homogeneity assumption for each background layer is used to address the ill-posed condition while maintaining accuracy for permittivity reconstruction, significantly reducing the number of unknowns. Using an appropriate initial guess for each layer, the post-CSI approach also provides the dielectric profile of a buried object. The finite difference time domain numerical tests show that the proposed approach significantly enhances reconstruction accuracy for buried objects compared with the traditional CSI approach.

The damage cost caused by malware has been increasing in the world. Usually, malwares are packed so that it is not detected. It is a hard task even for professional malware analysts to identify the packers especially when the malwares are multi-layer packed. In this letter, we propose a method to identify the packers for multi-layer packed malwares by using k-nearest neighbor algorithm with entropy-analysis for the malwares.

There have been lots of previous studies on fluency evaluation of spontaneous speech. However, most of them focus on lexical cues, and little emphasis is placed on how diverse acoustic features and deep end-to-end models contribute to improving the performance. In this paper, we describe multi-layer neural network to investigate not only lexical features extracted from transcription, but also consider utterance-level acoustic features from audio data. We also conduct the experiments to investigate the performance of end-to-end approaches with mel-spectrogram in this task. As the speech fluency evaluation task, we evaluate our proposed method in two binary classification tasks of fluent speech detection and disfluent speech detection. Speech data of around 10 seconds duration each with the annotation of the three classes of “fluent,” “neutral,” and “disfluent” is used for evaluation. According to the two way splits of those three classes, the task of fluent speech detection is defined as binary classification of fluent vs. neutral and disfluent, while that of disfluent speech detection is defined as binary classification of fluent and neutral vs. disfluent. We then conduct experiments with the purpose of comparative evaluation of multi-layer neural network with diverse features as well as end-to-end models. For the fluent speech detection, in the comparison of utterance-level disfluency-based, prosodic, and acoustic features with multi-layer neural network, disfluency-based and prosodic features only are better. More specifically, the performance improved a lot when removing all of the acoustic features from the full set of features, while the performance is damaged a lot if fillers related features are removed. Overall, however, the end-to-end Transformer+VGGNet model with mel-spectrogram achieves the best results. For the disfluent speech detection, the multi-layer neural network using disfluency-based, prosodic, and acoustic features without fillers achieves the best results. The end-to-end Transformer+VGGNet architecture also obtains high scores, whereas it is exceeded by the best results with the multi-layer neural network with significant difference. Thus, unlike in the fluent speech detection, disfluency-based and prosodic features other than fillers are still necessary in the disfluent speech detection.

We propose a target detection network (RMF-Net) based on the multi-scale strategy to solve the problems of large differences in the detection scale and mutual occlusion, which result in inaccurate locations. A multi-layer feature fusion module and multi-expansion dilated convolution pyramid module were designed based on the ResNet-101 residual network. The ability of the network to express the multi-scale features of the target could be improved by combining the shallow and deep features of the target and expanding the receptive field of the network. Moreover, RoI Align pooling was introduced to reduce the low accuracy of the anchor frame caused by multiple quantizations for improved positioning accuracy. Finally, an AD-IoU loss function was designed, which can adaptively optimise the distance between the prediction box and real box by comprehensively considering the overlap rate, centre distance, and aspect ratio between the boxes and can improve the detection accuracy of the occlusion target. Ablation experiments on the RMF-Net model verified the effectiveness of each factor in improving the network detection accuracy. Comparative experiments were conducted on the Pascal VOC2007 and Pascal VOC2012 datasets with various target detection algorithms based on convolutional neural networks. The results demonstrated that RMF-Net exhibited strong scale adaptability at different occlusion rates. The detection accuracy reached 80.4% and 78.5% respectively.

With the rapid progress of the integrated nanophotonics technology, the optical neural network architecture has been widely investigated. Since the optical neural network can complete the inference processing just by propagating the optical signal in the network, it is expected more than one order of magnitude faster than the electronics-only implementation of artificial neural networks (ANN). In this paper, we first propose an optical vector-matrix multiplication (VMM) circuit using wavelength division multiplexing, which enables inference processing at the speed of light with ultra-wideband. This paper next proposes optoelectronic circuit implementation for batch normalization and activation function, which significantly improves the accuracy of the inference processing without sacrificing the speed performance. Finally, using a virtual environment for machine learning and an optoelectronic circuit simulator, we demonstrate the ultra-fast and accurate operation of the optical-electronic ANN circuit.

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

Designing an optimum quantizer can be treated as the optimization problem of finding the quantization indices that minimize the quantization error. One solution to the optimization problem, DP quantization, is based on dynamic programming. Some applications, such as bit-depth scalable codec and tone mapping, require the construction of multiple quantizers with different quantization levels, for example, from 12bit/channel to 10bit/channel and 8bit/channel. Unfortunately, the above mentioned DP quantization optimizes the quantizer for just one quantization level. That is, it is unable to simultaneously optimize multiple quantizers. Therefore, when DP quantization is used to design multiple quantizers, there are many redundant computations in the optimization process. This paper proposes an extended DP quantization with a complexity reduction algorithm for the optimal design of multiple quantizers. Experiments show that the proposed algorithm reduces complexity by 20.8%, on average, compared to conventional DP quantization.

This paper proposes a dual-polarized metasurface that utilizes multi-layer ceramic capacitors (MLCCs) for radar cross-section (RCS) reduction in the 28GHz band of the quasi-millimeter band. MLCCs are very small in size; therefore, miniaturization of the unit cell structure of the metamaterial can be expected, and the MLCCs can be periodically loaded onto a narrow object. First, the MLCC structure was modeled as a basic structure, and the effective permeability of the MLCC was determined to investigate the influence of the arrangement direction on MLCC interaction. Next, the unit cell structure of the dual-polarized metasurface was designed for an MLCC set on a dielectric substrate. By analyzing the infinite periodic structure and finite structure, the monostatic reduction characteristics, oblique incidence characteristics, and dual-polarization characteristics of the proposed metasurface were evaluated. In the case of the MLCCs arranged in the same direction, the monostatic RCS reduction was approximately 30dB at 29.8GHz, and decreased when the MLCCs were arranged in a checkerboard pattern. The monostatic RCS reductions for the 5 × 5, 10 × 10, and 20 × 20 divisions were roughly the same, i.e., 10.8, 9.9, and 10.3dB, respectively. Additionally, to validate the simulated results, the proposed dual-polarized metasurface was fabricated and measured. The measured results were found to approximately agree with the simulated results, confirming that the RCS can be reduced for dual-polarization operation.

In this paper we design a fast fabric defect detection framework (Fast-DDF) based on gray histogram back-projection, which adopts end to end multi-convoluted network model to realize defect classification. First, the back-projection image is established through the gray histogram on fabric image, and the closing operation and adaptive threshold segmentation method are performed to screen the impurity information and extract the defect regions. Then, the defect images segmented by the Fast-DDF are marked and normalized into the multi-layer convolutional neural network for training. Finally, in order to solve the problem of difficult adjustment of network model parameters and long training time, some strategies such as batch normalization of samples and network fine tuning are proposed. The experimental results on the TILDA database show that our method can deal with various defect types of textile fabrics. The average detection accuracy with a higher rate of 96.12% in the database of five different defects, and the single image detection speed only needs 0.72s.

This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.

Recently, it has been reported that malicious third-party IC vendors often insert hardware Trojans into their products. Especially in IC design step, malicious third-party vendors can easily insert hardware Trojans in their products and thus we have to detect them efficiently. In this paper, we propose a machine-learning-based hardware-Trojan detection method for gate-level netlists using multi-layer neural networks. First, we extract 11 Trojan-net feature values for each net in a netlist. After that, we classify the nets in an unknown netlist into a set of Trojan nets and that of normal nets using multi-layer neural networks. By experimentally optimizing the structure of multi-layer neural networks, we can obtain an average of 84.8% true positive rate and an average of 70.1% true negative rate while we can obtain 100% true positive rate in some of the benchmarks, which outperforms the existing methods in most of the cases.

Arrhythmia classification based on electrocardiogram (ECG) is crucial in automatic cardiovascular disease diagnosis. The classification methods used in the current practice largely depend on hand-crafted manual features. However, extracting hand-crafted manual features may introduce significant computational complexity, especially in the transform domains. In this study, an accurate method for patient-specific ECG beat classification is proposed, which adopts morphological features and timing information. As to the morphological features of heartbeat, an attention-based two-level 1-D CNN is incorporated in the proposed method to extract different grained features automatically by focusing on various parts of a heartbeat. As to the timing information, the difference between previous and post RR intervels is computed as a dynamic feature. Both the extracted morphological features and the interval difference are used by multi-layer perceptron (MLP) for classifing ECG signals. In addition, to reduce memory storage of ECG data and denoise to some extent, an adaptive heartbeat normalization technique is adopted which includes amplitude unification, resolution modification, and signal difference. Based on the MIT-BIH arrhythmia database, the proposed classification method achieved sensitivity Sen=93.4% and positive predictivity Ppr=94.9% in ventricular ectopic beat (VEB) detection, sensitivity Sen=86.3% and positive predictivity Ppr=80.0% in supraventricular ectopic beat (SVEB) detection, and overall accuracy OA=97.8% under 6-bit ECG signal resolution. Compared with the state-of-the-art automatic ECG classification methods, these results show that the proposed method acquires comparable accuracy of heartbeat classification though ECG signals are represented by lower resolution.

Glial cells include several types of cells such as astrocytes, and oligodendrocytes apart from the neurons in the brain. In particular, astrocytes are known to be important in higher brain function and are therefore sometimes simply called glial cells. An astrocyte can transmit signals to other astrocytes and neurons using ion concentrations. Thus, we expect that the functions of an astrocyte can be applied to an artificial neural network. In this study, we propose a multi-layer perceptron (MLP) with a pulse glial chain. The proposed MLP contains glia (astrocytes) in a hidden layer. The glia are connected to neurons and are excited by the outputs of the neurons. The excited glia generate pulses that affect the excitation thresholds of the neurons and their neighboring glia. The glial network provides a type of positional relationship between the neurons in the hidden layer, which can enhance the performance of MLP learning. We confirm through computer simulations that the proposed MLP has better learning performance than a conventional MLP.

Multi-layer transport networks that utilize sub-lambda paths over a wavelength path have been shown to be effective in accommodating traffic with various levels of granularity. For different service requirements, a virtualized network was proposed where the infrastructure is virtually sliced to accommodate different levels of reliability. On the other hand, network reconfiguration is a promising candidate for quasi-dynamic and multi-granular traffic. Reconfiguration, however, incurs some risks such as service disruption and fluctuations in delay. There has not yet been any study on accommodating and reconfiguring paths according to different service classes in multi-layer transport networks. In this paper, we propose differentiated reconfiguration to address the trade-off relationship between accommodation efficiency and disruption risk in virtualized multi-layer transport networks that considers service classes defined as a combination of including or excluding a secondary path and allowing or not allowing reconfiguration. To implement the proposed network, we propose a multi-layer redundant path accommodation design and reconfiguration algorithm. A reliability evaluation algorithm is also introduced. Numerical evaluations show that when all classes are divided equally, equipment cost can be reduced approximately by 6%. The proposed reconfigurable networks are shown to be a cost effective solution that maintains reliability.

This paper describes an architectural design and related services of a new Japanese academic backbone network, called SINET5, which will be launched in April 2016. The network will cover all 47 prefectures with 100-Gigabit Ethernet technology and connect each pair of prefectures with a minimized latency. This will enable users to leverage evolving cloud-computing powers as well as draw on a high-performance platform for data-intensive applications. The transmission layer will form a fully meshed, SDN-friendly, and reliable network. The services will evolve to be more dynamic and cloud-oriented in response to user demands. Cyber-security measures for the backbone network and tools for performance acceleration and visualization are also discussed.

In this letter, we present a new method of alleviating the deterioration in the quality of real-time video service during vertical handover (VHO). The proposed method stochastically delays the starting time of the service disruption of VHO in order to reduce the number of lost frames caused by the inter-frame dependency of multi-layered video traffic. The results show that the proposed method significantly decreases the average frame loss time at the sacrifice of an increased handover execution time by one half of the group of picture (GOP) interval of the video traffic.

This paper presents a printed circuit board (PCB) integrated multi-layered strip line tandem coupler, which used simple compensating ground through-hole (GTH) elements. The GTH elements on one end of the coupled line can generate additional capacitance between the signal line and the ground, which effectively compensates for the parasitic capacitance around the crossed signal lines on the opposite end of the coupled line. It has been experimentally demonstrated that the proposed coupler fabricated for the X-band is effective to improve both the reflection and the isolation characteristics.

This letter studies the simple dynamic binary neural network characterized by signum activation function and ternary connection parameters. In order to control the sparsity of the connections and the stability of the stored signal, a simple evolutionary algorithm is presented. As a basic example of teacher signals, we consider a binary periodic orbit which corresponds to a control signal of ac-dc regulators. In the numerical experiment, applying the correlation-based learning, the periodic orbit can be stored. The sparsification can be effective to reinforce the stability of the periodic orbit.

Modern field programmable gate arrays (FPGAs) with heterogeneous resources are partially reconfigurable. Existing methods of reconfiguration-aware floorplanning have limitations with regard to homogeneous resources; they solve only a part of the reconfigurable problem. In this paper, first, a precise model for partially reconfigurable FPGAs is formulated, and then, a two-phase floorplanning approach is presented. In the proposed approach, resource distribution is taken into consideration at all times. In the first step, a resource-aware insertion-after-remove perturbation is devised on the basis of the multi-layer sequence pair constraint graphs, and resource-aware slack-based moves (RASBM) are made to satisfy resource requirements. In the second step, a resource-aware fixed-outline floorplanner is used, and RASBM are applied to pack the reconfigurable regions on the FPGAs. Experimental results show that the proposed approach is resource- and reconfiguration-aware, and facilitates stable floorplanning. In addition, it reduces the wire-length by 4–28% in the first step, and by 12% on average in the second step compared to the wire-length in previous approaches.

This paper proposes optical node architectures for the single-layer optical cross-connect (OXC) and hierarchical OXC (HOXC) that utilize dedicated add/drop switches for originating/terminating traffic at a node. For both single-layer OXC and HOXC, three architectures with different restrictions on add/drop capabilities are presented. The performance of the proposed architectures is compared through numerical experiments. The architectures significantly reduce total switch scale and minimize necessary switch size while attaining colorless, directionless and contentionless capabilities.