The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the V_DD terminal of SRAM. It is newly found that | V_TH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

This paper introduces the basics of energy harvesters and demonstrates two specific vibratory-type energy harvesters developed at the University of Hyogo. The fabrication and evaluation results of the vibratory-type energy harvesters, which employ electrostatic and electromagnetic mechanisms, are described. The aim of developing these devices is to realize a power source for an autonomous human monitoring system. The results of harvesting from actual human activities obtained using a data logger are also described. Moreover, challenges in the power management of electronic circuitry used for energy harvesting are briefly discussed.

We present a multiband LTE SAW-less CMOS transmitter with source-follower-driven passive mixers, envelope-tracked RF-programmable gain amplifiers (RF-PGAs), and Marchand Baluns. A driver stage for passive mixers is realized by a source follower, which enables a quadrature modulator (QMOD) to achieve low noise performance at a 1.2 V supply and contributes to a small-area and low-power transmitter. An envelope-tracking technique is adopted to improve the linearity of RF-PGAs and obtain a better Evolved Universal Terrestrial Radio Access Adjacent Channel Leakage power Ratio (E-UTRA ACLR). The Marchand balun covers more frequency bands than a transformer and is more suitable for multiband operation. The proposed transmitter, which also includes digital-to-analog converters and a phase-locked loop, is implemented in a 65-nm CMOS process. The implemented transmitter achieves E-UTRA ACLR of less than -42 dBc and RX-band noise of less than -158 dBc/Hz in the frequency range of 700 MHz–2.6 GHz. These performances are good enough for multiband LTE and SAW-less operation.

TransferJet^TM is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer up to 522 Mbps within a few centimeters range. We present a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. Baseband filtering techniques for a transmitter (TX) and a receiver (RX) are proposed in order to handle the ultra-wide bandwidth with low power consumption and small area. A programmable power attenuator (PAT) for precise output power is also proposed in this paper. The SoC achieves energy efficiencies of 0.19 nJ/bit and 0.43 nJ/bit for the TX and the RX, respectively. The RX sensitivity of -70 dBm for 522 Mbps data rate and the TX error vector magnitude (EVM) of -31 dB are achieved.

A wide-tuning-range LC-tuned voltage-controlled oscillator (LC-VCO) – featuring small VCO-gain (K_VCO) variation – has been developed. For small K_VCO variation, a serial LC-resonator that consists of an inductor, a fine-tuning varactor, and a capacitor bank was added to a conventional parallel LC-resonator that uses a capacitor bank scheme. The resonator was applied to a 3.9-GHz VCO for multi-band W-CDMA RFIC fabricated using 0.25-µm Si-BiCMOS technology. The VCO exhibited K_VCO variation of only 21%, which is one third that of a conventional VCO, with a 34% tuning range. The VCO also exhibited a low phase noise of -121 dBc/Hz at 1-MHz offset frequency and a low current consumption of 6.0 mA.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of -181.3 dBc/Hz is achieved.

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.

An ultra low power and low voltage successive-approximation-register (SAR) analog-to-digital converter (ADC) with timing optimized asynchronous clock generator is presented. By calibrating the delay amount of the clock generator, the DAC settling waiting time is adaptively optimized to counter the device mismatch. This technique improved the maximum sampling frequency by 40% keeping ENOB around 7-bit at 0.4 V analog and 0.7 V digital power supply voltage. The delay time dependency on power supply has small effect to the accuracy of conversion. Decreasing of supply voltage by 9% degrades ENOB only by 0.1-bit, and the proposed calibration can give delay margins for high voltage swing. The prototype ADC fabricated in 40 nm CMOS process achieved figure of merit (FoM) of 8.75-fJ/conversion-step with 2.048 MS/s at 0.6 V analog and 0.7 V digital power supply voltage. The ADC can operates from 50 S/s to 8 MS/s keeping ENOB over 7.5-bit.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.

This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for such as communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm².

Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65 nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, ≤ -55 dB with a 100 MHz input, and +10.3 dBm, respectively, all with a ± 0.1 Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60 mW in the case of a 1.2 V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies.

Substrate coupling of radio frequency (RF) components is represented by equivalent circuits unifying a resistive mesh network with lumped capacitors in connection with the backside of device models. Two-port S-parameter test structures are used to characterize the strength of substrate coupling of resistors, capacitors, inductors, and MOSFETs in a 65 nm CMOS technology with different geometries and dimensions. The consistency is finely demonstrated between simulation with the equivalent circuits and measurements of the test structures, with the deviation of typically less than 3 dB for passive and 6 dB for active components, in the transmission properties for the frequency range of interest up to 8 GHz.

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.

Recent attempts to directly combine CMOS pixel readout chips with modern gas detectors open the possibility to fully take advantage of gas detectors. Those conventional readout LSIs designed for hybrid semiconductor detectors show some issues when applied to gas detectors. Several new proposed readout LSIs can improve the time and the charge measurement precision. However, the widely used basic charge sensitive amplifier (CSA) has an almost fixed dynamic range. There is a trade-off between the charge measurement resolution and the detectable input charge range. This paper presents a method to apply the folding integration technique to a basic CSA. As a result, the detectable input charge dynamic range is expanded while maintaining all the key merits of a basic CSA. Although folding integration technique has already been successfully applied in CMOS image sensors, the working conditions and the signal characteristics are quite different for pixel readout LSIs for gas particle detectors. The related issues of the folding CSA for pixel readout LSIs, including the charge error due to finite gain of the preamplifier, the calibration method of charge error, and the dynamic range expanding efficiency, are addressed and analyzed. As a design example, this paper also demonstrates the application of the folding integration technique to a Qpix readout chip. This improves the charge measurement resolution and expands the detectable input dynamic range while maintaining all the key features. Calculations with SPICE simulations show that the dynamic range can be improved by 12 dB while the charge measurement resolution is improved by 10 times. The charge error during the folding operation can be corrected to less than 0.5%, which is sufficient for large input charge measurement.

We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

In this paper, a systematic design of X-band (9–10 GHz) 40 W pulse-driven GaN HEMT power amplifier is presented. The design includes device evaluation, verification of designed matching circuits, and measurements of the designed power amplifier. Firstly, the optimum input and output impedances for the selected GaN HEMT chip from TriQuint Semiconductor Inc. are evaluated using load-pull measurement. The selected GaN HEMT shows extremely low optimum impedances, which are obtained using a pre-match load-pull method due to the limitation of the tuning impedance range of conventional impedance tuners. We propose a novel extraction of the optimum impedances with general pre-match circuits. The extracted optimum impedances are found to be close to those computed, using the large signal model supplied from TriQuint Semiconductor. Using the optimum impedances, the matching circuits of the power amplifier are designed employing the combined impedance transformer type based on EM co-simulation. The fabricated power amplifier has a size of 1517.8 mm², an efficiency above 45%, power gain of 7.7–9.9 dB and output power of 47–44.8 dBm at 9–10 GHz with pulse width of 10 µsec and duty of 10%.

A technique that enables a SSCG to fine-tune an output signal frequency and a spread ratio is presented. Proposed SSCG achieves the output signal frequency from 1.2 GHz to 3.0 GHz and the spread ratio from 0 to 30000 ppm. The fine-tuning technique achieves 30 ppm adjustment of the output signal frequency and 200 ppm adjustment of the spread ratio. This technique is achieved by controlling a triangular modulation signal characteristics generated by a proposed digital controlled wave generator. A proposed multi-modulus divider can have a divide ratio of 4/5 and 8/9. This SSCG has been fabricated in a 0.13-µm CMOS process. The output signal frequency-range and the spread ratio are achieved fluently from 0.1 to 3.0 GHz and from 0 to 30000 ppm, respectively. EMI noise is suppressed at less than 17.1 dB at the output signal frequency of 3.0 GHz and spread ratio of 30000 ppm.

A 5.6-GHz 1-V balanced LC-tank Colpitts voltage controlled oscillator is designed and implemented with a TSMC 0.18-µm CMOS process. This proposed Colpitts VCO circuit adopts two single-ended complementary LC-tank VCOs coupled by two pairs of varactors. The proposed VCO operates at low power consumption because it has the same dc current path as the np-MOSFETs. The Measured results of the proposed VCO achieve tuning range of 670 MHz from 5.23 to 5.9 GHz while the controlled voltage is tuned from 0 to 1-V, phase noise of -118.8 dBc/Hz at 1 MHz offset frequency from the carrier of 5.6 GHz and output power of -10.97 dBm at the supply voltage of 1 V. The power consumption of the core circuit is 1.79 mW and the chip area including pads is 0.451 (0.55 0.82) mm².